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公开(公告)号：US08665005B2
公开(公告)日：2014-03-04
申请号：US13310541
申请日：2011-12-02
申请人： Danilo Gerna , Enrico Sacchi
发明人： Danilo Gerna , Enrico Sacchi
IPC分类号： G05F1/10
摘要： The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.
摘要翻译： 逆变器的转换频率随其内部晶体管的跨导而变化，作为温度和偏置电平的函数。 为了保持恒定的跨越温度的转换频率，并且因此降低由逆变器引入的相位噪声变化，系统，方法和电路被公开用于使温度变化电流偏置逆变器，使得晶体管的跨导在温度保持恒定的同时保持 这样做最低的功耗。 各种实施例可以包括使用具有比例绝对温度（PTAT）装置的电流源。
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公开(公告)号：US20120139617A1
公开(公告)日：2012-06-07
申请号：US13310541
申请日：2011-12-02
申请人： Danilo Gerna , Enrico Sacchi
发明人： Danilo Gerna , Enrico Sacchi
IPC分类号： H03K19/003
摘要： The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.
摘要翻译： 逆变器的转换频率随其内部晶体管的跨导而变化，作为温度和偏置电平的函数。 为了保持恒定的跨越温度的转换频率，并且因此降低由逆变器引入的相位噪声变化，系统，方法和电路被公开用于使温度变化电流偏置逆变器，使得晶体管的跨导在温度保持恒定的同时保持 这样做最低的功耗。 各种实施例可以包括使用具有比例绝对温度（PTAT）装置的电流源。
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公开(公告)号：US20120027121A1
公开(公告)日：2012-02-02
申请号：US13194089
申请日：2011-07-29
申请人： Danilo Gerna , Stefano Dal Toso , Gregory Uehara
发明人： Danilo Gerna , Stefano Dal Toso , Gregory Uehara
CPC分类号： H04B1/0483 , H03B19/00 , H03K23/667 , H03L7/18 , H04B2001/0491
摘要： A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of the plurality of second frequency dividers includes a second plurality of components and is configured to divide the input frequency of the input signal to generate a second signal having the first frequency and a second phase. The control module is configured to connect the second plurality of components of one of the second frequency dividers to the first plurality of components of the first frequency divider.
摘要翻译： 一种包括第一分频器，多个第二分频器和控制模块的系统。 第一分频器包括第一多个分量，并且被配置为分割输入信号的输入频率以产生具有第一频率和第一相位的第一信号。 多个第二分频器中的每一个包括第二多个分量，并且被配置为分割输入信号的输入频率以产生具有第一频率和第二相位的第二信号。 控制模块被配置为将第二分频器之一的第二多个分量连接到第一分频器的第一多个分量。
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4.发明授权Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory 有权用于非易失性存储器和多级非易失性存储器的多级编程的方法
公开(公告)号：US06011715A
公开(公告)日：2000-01-04
申请号：US185906
申请日：1998-11-03
CPC分类号： G11C11/5621 , G11C11/5628
摘要： A programming method for a nonvolatile memory includes the steps of: a) determining a current value of the threshold voltage; b) acquiring a target value of the threshold voltage; c) calculating a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying a second number of consecutive voltage pulses to the gate terminal of the cell, the second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring a current value of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.
摘要翻译： 一种用于非易失性存储器的编程方法包括以下步骤：a）确定阈值电压的当前值; b）获取阈值电压的目标值; c）计算将阈值电压从当前值到目标值所需的第一数量的栅极电压脉冲; d）将第二数量的连续电压脉冲施加到所述单元的栅极端子，所述第二数量与所述第一数量相关并具有均匀增加的幅度; e）然后测量阈值电压的当前值; 并重复步骤c）至e），直到获得最终阈值。
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5.发明授权
公开(公告)号：US5805492A
公开(公告)日：1998-09-08
申请号：US722572
申请日：1996-09-27
申请人： Danilo Gerna , Marco Pasotti , Stefano Marchese
发明人： Danilo Gerna , Marco Pasotti , Stefano Marchese
CPC分类号： G11C27/00 , G11C27/024
摘要： The speed of a capacitive cell RAAM used for storing an optical image as electric charge is greatly enhanced by presampling the serial analog input signal on two rows or lines of presampling capacitors, each composed of the same number of capacitors as the number of columns of the capacitive cell RAAM and by "writing" in a parallel mode the selected row of said memory. The values stored in the capacitors of one of said two presampling rows are transferred (written) in the corresponding cells of the selected row of the memory while presampling continues on the other row of presampling capacitors.
摘要翻译： 用于存储光学图像作为电荷的电容单元RAAM的速度通过对两行或两行预采样电容器的串行模拟输入信号进行预取样来大大增强，每个或两行预采样电容器由相同数量的电容器组成， 电容单元RAAM，并通过所述存储器的所选行以并行模式“写入”。 存储在所述两个预采样行中的一个的电容器中的值被传送（写入）到存储器的选定行的相应单元中，同时在另一行预采样电容器上继续进行预采样。
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6.发明授权Method and device for analog programming of flash EEPROM memory cells with autoverify 有权用于自动验证的闪存EEPROM存储单元的模拟编程方法和设备
公开(公告)号：US6081448A
公开(公告)日：2000-06-27
申请号：US162639
申请日：1998-09-28
CPC分类号： G11C27/005
摘要： A device for analog programming is disclosed. The device comprises a current mirror circuit connected to drain terminals of a cell to be programmed and of a MOS reference transistor. An operational amplifier has inputs connected to the drain terminals of the cell and respectively of the MOS transistor and an output connected to the control terminal of the MOS transistor. During programming, the control and drain terminals of the cell are biased at corresponding programming voltages and the output voltage of the operational amplifier, which is correlated to the current threshold voltage level of the cell, is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.
摘要翻译： 公开了一种用于模拟编程的装置。 该器件包括连接到要编程的单元的漏极端子和MOS参考晶体管的电流镜电路。 运算放大器具有连接到单元的漏极端子和MOS晶体管的漏极端子和连接到MOS晶体管的控制端子的输出的输入。 在编程期间，单元的控制和漏极端子以相应的编程电压被偏置，并且监视与电池的当前阈值电压电平相关的运算放大器的输出电压，并且当该输出电压 变得至少等于与小区所需的阈值相关的参考电压。
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公开(公告)号：US08442462B2
公开(公告)日：2013-05-14
申请号：US13194089
申请日：2011-07-29
申请人： Danilo Gerna , Stefano Dal Toso , Gregory Uehara
发明人： Danilo Gerna , Stefano Dal Toso , Gregory Uehara
IPC分类号： H04B1/04
CPC分类号： H04B1/0483 , H03B19/00 , H03K23/667 , H03L7/18 , H04B2001/0491
摘要： A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of the plurality of second frequency dividers includes a second plurality of components and is configured to divide the input frequency of the input signal to generate a second signal having the first frequency and a second phase. The control module is configured to connect the second plurality of components of one of the second frequency dividers to the first plurality of components of the first frequency divider.
摘要翻译： 一种包括第一分频器，多个第二分频器和控制模块的系统。 第一分频器包括第一多个分量，并且被配置为分割输入信号的输入频率以产生具有第一频率和第一相位的第一信号。 多个第二分频器中的每一个包括第二多个分量，并且被配置为分割输入信号的输入频率以产生具有第一频率和第二相位的第二信号。 控制模块被配置为将第二分频器之一的第二多个分量连接到第一分频器的第一多个分量。
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8.发明授权公开(公告)号：US06195283B1
公开(公告)日：2001-02-27
申请号：US09076013
申请日：1998-05-11
IPC分类号： G11C700
CPC分类号： G11C27/005
摘要： For each memory cell to be programmed, the present threshold value of the cell is determined; the desired threshold value is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells of a memory array which is connected to a single word line and to different bit lines, each with a programming pulse the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.
摘要翻译： 对于要编程的每个存储器单元，确定单元的当前阈值; 获取期望的阈值; 计算当前阈值与期望阈值之间的模拟距离; 然后产生编程脉冲，其持续时间与计算出的模拟距离成比例。 重复编程和读取周期，直到达到所需的阈值。 由于中间读取步骤数量的减少，可以节省时间。 该方法允许并行地编程存储器阵列的多个单元，其连接到单个字线和不同的位线，每个存储器阵列的编程脉冲的持续时间与为同一个字线计算的模拟距离成比例 细胞。 编程过程非常快，因为编程的并行应用和中间阅读周期的节省。
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9.发明授权Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMS 有权用于非易失性存储器件，特别是闪速存储器和EEPROMS的并行编程的方法
公开(公告)号：US6069822A
公开(公告)日：2000-05-30
申请号：US181230
申请日：1998-10-27
CPC分类号： G11C16/3459 , G11C16/3454
摘要： The programming method comprises the steps of applying a programming pulse to a first cell and simultaneously verifying the present threshold value of at least a second cell; then verifying the present threshold value of the first cell and simultaneously applying a programming pulse to the second cell. In practice, during the entire programming operation, the gate terminal of both the cells is biased to a same predetermined gate voltage and the source terminal is connected to ground; the step of applying a programming pulse is carried out by biasing the drain terminal of the cell to a predetermined programming voltage and the step of verifying is carried out by biasing the drain terminal of the cell to a read voltage different from the programming voltage. Thereby, switching between the step of applying a programming pulse and verifying is obtained simply by switching the drain voltage of the cells.
摘要翻译： 编程方法包括以下步骤：将编程脉冲施加到第一单元并且同时验证至少第二单元的当前阈值; 然后验证第一小区的当前阈值并同时向第二小区施加编程脉冲。 实际上，在整个编程操作期间，两个单元的栅极端子被偏置到相同的预定栅极电压，并且源极端子接地; 通过将单元的漏极端子偏置到预定的编程电压来执行编程脉冲的步骤，并且通过将单元的漏极端子偏压到与编程电压不同的读取电压来执行验证步骤。 因此，简单地通过切换单元的漏极电压来获得施加编程脉冲和验证的步骤之间的切换。
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10.发明授权High-precision analog reading circuit for flash analog memory arrays using negative feedback 失效用于闪存模拟存储器阵列的高精度模拟读取电路使用负反馈
公开(公告)号：US6016272A
公开(公告)日：2000-01-18
申请号：US60165
申请日：1998-04-14
CPC分类号： G11C16/28 , G11C27/005
摘要： An analog reading circuit having a current mirror circuit forcing two identical currents into a cell to be read and into a reference cell. An operational amplifier has an inverting input connected to the drain terminal of the cell to be read, a non-inverting input connected to the drain terminal of the reference cell, and an output connected to the gate terminal of the reference cell. The reference cell therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell to be read and the reference cell constant, irrespective of temperature variations. The reading circuit is also of high precision and has a high reading speed.
摘要翻译： 一种具有电流镜像电路的模拟读取电路，其将两个相同的电流强制进入待读取的单元并进入参考单元。 运算放大器具有连接到要读取的单元的漏极端子的反相输入端，连接到参考单元的漏极端子的非反相输入端和连接到参考单元栅极端子的输出端。 因此，参考单元形成负反馈回路的一部分，其保持要读取的单元的过驱动电压和参考单元恒定，而与温度变化无关。 读取电路也具有高精度，读取速度快。
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