公开(公告)号：US06590407B2

公开(公告)日：2003-07-08

申请号：US10222113

申请日：2002-08-16

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US06255838B1

公开(公告)日：2001-07-03

申请号：US09567796

申请日：2000-05-09

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US06255837B1

公开(公告)日：2001-07-03

申请号：US09567632

申请日：2000-05-09

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the sane or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备处检测到合格或其他信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US06646459B2

公开(公告)日：2003-11-11

申请号：US09813130

申请日：2001-03-19

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US6160413A

公开(公告)日：2000-12-12

申请号：US222674

申请日：1998-12-29

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R31/28 ,  G01R31/317

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 测试模式锁存电路驻留在具有测试电路和具有使能状态和禁止状态的操作电路的集成电路上。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US06570400B2

公开(公告)日：2003-05-27

申请号：US10113995

申请日：2002-03-29

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US5627478A

公开(公告)日：1997-05-06

申请号：US498823

申请日：1995-07-06

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R31/28 ,  G01R31/317

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state test key inputs are not latched, and thus, test modes are not entered. Initially the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路很容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。