公开(公告)号：US07793261B1

公开(公告)日：2010-09-07

申请号：US09411792

申请日：1999-10-01

申请人： David Alan Edwards ,  Margaret Rose Gearty ,  Glenn A. Farrall ,  Atsushi Hasegawa ,  Anthony Willis Rich

发明人： David Alan Edwards ,  Margaret Rose Gearty ,  Glenn A. Farrall ,  Atsushi Hasegawa ,  Anthony Willis Rich

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F11/261 ,  G06F11/3656

摘要： An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

摘要翻译： 提供一种包括处理器和调试电路的微计算机，该调试电路包括专用链路，该专用链路在处理器和调试电路之间传送信息以支持调试操作 在一个方面，处理器提供存储在调试电路的存储器映射寄存器中的程序计数器信息。 程序计数器信息可以是处理器管线的回写阶段处理器程序计数器的值。 此外，包括消息信息的跟踪信息通过专用链路以非侵入方式传送。 一方面，微型计算机被实现为单个集成电路。

公开(公告)号：US06859891B2

公开(公告)日：2005-02-22

申请号：US09410606

申请日：1999-10-01

申请人： David Alan Edwards ,  Margaret Rose Gearty ,  Bernard Ramanadin ,  Anthony Willis Rich

发明人： David Alan Edwards ,  Margaret Rose Gearty ,  Bernard Ramanadin ,  Anthony Willis Rich

IPC分类号： G06F11/36 ,  G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3648 ,  G06F11/3656

摘要： An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

摘要翻译： 提供一种包括处理器和调试电路的微计算机，该调试电路包括专用链路，该专用链路在处理器和调试电路之间传送信息以支持调试操作 在一个方面，处理器提供存储在调试电路的存储器映射寄存器中的程序计数器信息。 程序计数器信息可以是处理器管线的回写阶段处理器程序计数器的值。 此外，包括消息信息的跟踪信息通过专用链路以非侵入方式传送。 一方面，微型计算机被实现为单个集成电路。

公开(公告)号：US06477638B1

公开(公告)日：2002-11-05

申请号：US09410637

申请日：1999-10-01

申请人： Margaret Rose Gearty ,  Chih-Jui Peng

发明人： Margaret Rose Gearty ,  Chih-Jui Peng

IPC分类号： G06F15163

CPC分类号： G06F9/3877 ,  G06F9/3867

摘要： A computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU pipeline including a plurality of pipestages and the FPU pipeline including a plurality of pipestages, wherein each CPU pipestage in the CPU pipeline has a corresponding pipestage in the FPU pipeline, a method of synchronizing operation of the CPU pipeline and the FPU pipeline, the method including the steps of (a) receiving an instruction in a first CPU pipestage, (b) receiving the instruction in a corresponding first FPU pipestage, (c) processing the instruction in the first CPU pipestage, (d) processing the instruction in the first FPU pipestage, (e) generating, by the first CPU pipestage, a first signal indicating that the instruction has been processed by first CPU pipestage and is ready to proceed to a second pipestage in the CPU pipeline, (f) generating by the first FPU pipestage, a second signal indicating that the instruction has been processed by the first FPU pipestage and is ready to proceed to a second pipestage in the FPU pipeline, (g) sending the instruction from the first CPU pipestage to the second pipestage in the CPU pipeline, (h) sending the instruction from the first FPU pipestage to the second pipestage in the FPU pipeline, (i) wherein the second pipestage in the CPU pipeline responds to the second signal to send the instruction to a third pipestage in the CPU pipeline, and (j) wherein the second pipestage in the FPU pipeline responds to the first signal to send the instruction to a third pipestage in the FPU pipeline. A corresponding apparatus is also provided.

摘要翻译： 一种具有中央处理单元（CPU）执行流水线和浮点单元（FPU）执行流水线的计算机系统，所述CPU流水线包括多个管道，并且所述FPU流水线包括多个管道，其中CPU流水线中的每个CPU分支 在FPU流水线中具有相应的管道，一种使CPU流水线和FPU流水线的运行同步的方法，该方法包括以下步骤：（a）在第一CPU流水线中接收指令，（b）接收相应的指令 （c）处理第一个CPU分支中的指令，（d）处理第一个FPU分支中的指令，（e）通过第一个CPU分支产生指示该指令已被处理的第一个信号 第一个CPU分支，并准备进入CPU流水线中的第二个分支管道，（f）通过第一个FPU分支生成第二个信号，指示该指令已经处理 d通过第一个FPU分支，并准备进入FPU流水线中的第二个分支管道，（g）将指令从第一个CPU分支发送到CPU流水线中的第二个分支管道，（h）从第一个FPU发送指令 （i）其中CPU流水线中的第二管道响应于第二信号以将指令发送到CPU管线中的第三管道，以及（j）其中FPU中的第二管道 管道响应第一个信号，将指令发送到FPU管道中的第三个管道。 还提供了相应的装置。

公开(公告)号：US06542983B1

公开(公告)日：2003-04-01

申请号：US09410925

申请日：1999-10-01

申请人： Margaret Rose Gearty ,  Chih-Jui Peng

发明人： Margaret Rose Gearty ,  Chih-Jui Peng

IPC分类号： G06F900

CPC分类号： G06F9/3875 ,  G06F9/3867 ,  G06F9/3877

摘要： In a computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline including a CPU decoder pipestage and the FPU execution pipeline including an FPU decoder pipestage, the method including the steps of, (a) sending a first instruction to the CPU decoder pipestage, (b) sending the first instruction to the FPU decoder pipestage, (c) generating a signal indicating that the first instruction has been accepted by the CPU decoder pipestage, (d) generating a signal indicating that the first instruction has been accepted by the FPU decoder pipestage, (e) sending a second instruction to the CPU decoder pipestage in response to step (d), and (f) sending a second instruction to the FPU decoder pipestage in response to step (c). A corresponding apparatus is also provided.

摘要翻译： 在具有中央处理单元（CPU）执行流水线和浮点单元（FPU）执行流水线的计算机系统中，CPU执行流水线包括CPU解码器管道和包括FPU解码器管道的FPU执行流水线，该方法包括步骤 （a）向CPU解码器分支发送第一指令，（b）将第一指令发送到FPU解码器分支，（c）产生指示第一指令已被CPU解码器分支接收的信号，（d 产生指示第一指令已被FPU解码器分支接收的信号，（e）响应于步骤（d）向CPU解码器分支发送第二指令，以及（f）向FPU解码器发送第二指令 响应于步骤（c）的分支。 还提供了相应的装置。