-
公开(公告)号：US06859891B2
公开(公告)日：2005-02-22
申请号：US09410606
申请日：1999-10-01
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656
摘要： An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.
摘要翻译： 提供一种包括处理器和调试电路的微计算机，该调试电路包括专用链路，该专用链路在处理器和调试电路之间传送信息以支持调试操作 在一个方面，处理器提供存储在调试电路的存储器映射寄存器中的程序计数器信息。 程序计数器信息可以是处理器管线的回写阶段处理器程序计数器的值。 此外，包括消息信息的跟踪信息通过专用链路以非侵入方式传送。 一方面，微型计算机被实现为单个集成电路。
-
公开(公告)号：US07793261B1
公开(公告)日：2010-09-07
申请号：US09411792
申请日：1999-10-01
申请人： David Alan Edwards , Margaret Rose Gearty , Glenn A. Farrall , Atsushi Hasegawa , Anthony Willis Rich
发明人： David Alan Edwards , Margaret Rose Gearty , Glenn A. Farrall , Atsushi Hasegawa , Anthony Willis Rich
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/261 , G06F11/3656
摘要： An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.
摘要翻译： 提供一种包括处理器和调试电路的微计算机，该调试电路包括专用链路，该专用链路在处理器和调试电路之间传送信息以支持调试操作 在一个方面，处理器提供存储在调试电路的存储器映射寄存器中的程序计数器信息。 程序计数器信息可以是处理器管线的回写阶段处理器程序计数器的值。 此外，包括消息信息的跟踪信息通过专用链路以非侵入方式传送。 一方面，微型计算机被实现为单个集成电路。
-
公开(公告)号：US06601189B1
公开(公告)日：2003-07-29
申请号：US09410732
申请日：1999-10-01
IPC分类号： G06F1100
CPC分类号： G01R31/31903 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
摘要翻译： 提供了一种与集成电路通信的系统和方法，其允许集成电路与外部系统通信调试信息和系统总线事务信息。 该系统可以包括在集成电路和外部系统之间提供流量控制的接口协议。 系统可以包括用于传送信息的高速链路和/或JTAG链路。 链路可以由调试电路自动选择，或由片上设备或外部系统选择。 高速链路可实时追踪跟踪信息。 链路可以是存储器映射的，使得连接到系统总线的片上设备和其他设备可以访问外部系统。 高速链路也可以以与处理器或系统总线的速率整体耦合的速率工作。 此外，高速链路可以适应于响应于系统总线或处理器的操作速度的变化来改变速度。 JTAG接口可以使用标准的JTAG组件和指令，使得诸如使用这些组件和指令的调试适配器的外部设备可以被重新用于不同的集成电路类型。 通过JTAG或高速链路发送的信息可以被压缩以优化链路的可用带宽。 此外，处理器控制信号可以通过允许外部系统操纵和监视处理器及其相关模块的操作的链路传送。
-
公开(公告)号：US06591369B1
公开(公告)日：2003-07-08
申请号：US09410638
申请日：1999-10-01
IPC分类号： G06F1342
CPC分类号： G06F11/3636 , G01R31/31903 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
-
公开(公告)号：US06918065B1
公开(公告)日：2005-07-12
申请号：US09411794
申请日：1999-10-01
CPC分类号： G06F11/348
摘要： A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
摘要翻译： 提供用于执行非侵入性跟踪的系统，其从一个或多个处理器接收跟踪信息。 跟踪系统可以由用户配置为以各种模式操作以灵活地存储或发送跟踪信息。 跟踪系统包括一个内存映射的FIFO，可以在不影响处理器性能的情况下被访问。 在一个方面，跟踪系统包括跟踪缓冲器，其以处理器的内部时钟速度接收跟踪信息。 在另一个实施例中，提供了压缩协议，用于在将消息发送到外部系统之前或在存储器中存储消息的情况下在片上缓存跟踪消息。
-
公开(公告)号：US06684348B1
公开(公告)日：2004-01-27
申请号：US09409612
申请日：1999-10-01
IPC分类号： B06F1100
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
摘要翻译： 提供用于执行非侵入性跟踪的系统，其从一个或多个处理器接收跟踪信息。 跟踪系统可以由用户配置为以各种模式操作以灵活地存储或发送跟踪信息。 跟踪系统包括一个内存映射的FIFO，可以在不影响处理器性能的情况下被访问。 在一个方面，跟踪系统包括跟踪缓冲器，其以处理器的内部时钟速度接收跟踪信息。 在另一个实施例中，提供了压缩协议，用于在将消息发送到外部系统之前或在存储器中存储消息的情况下在片上缓存跟踪消息。
-
公开(公告)号：US06567932B2
公开(公告)日：2003-05-20
申请号：US09411795
申请日：1999-10-01
IPC分类号： G06F1100
CPC分类号： G06F11/364 , G06F11/25 , G06F11/267 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
-
公开(公告)号：US06530047B1
公开(公告)日：2003-03-04
申请号：US09411815
申请日：1999-10-01
IPC分类号： G01R3128
CPC分类号： G01R31/31903
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.
-
公开(公告)号：US06615370B1
公开(公告)日：2003-09-02
申请号：US09410560
申请日：1999-10-01
IPC分类号： G06F1100
CPC分类号： G06F11/3648 , G06F11/3636
摘要： A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
摘要翻译： 提供用于执行非侵入性跟踪的系统，其从一个或多个处理器接收跟踪信息。 跟踪系统可以由用户配置为以各种模式操作以灵活地存储或发送跟踪信息。 跟踪系统包括一个内存映射的FIFO，可以在不影响处理器性能的情况下被访问。 在一个方面，跟踪系统包括跟踪缓冲器，其以处理器的内部时钟速度接收跟踪信息。 在另一个实施例中，提供了压缩协议，用于在将消息发送到外部系统之前或在存储器中存储消息的情况下在片上缓存跟踪消息。
-
公开(公告)号：US06557119B1
公开(公告)日：2003-04-29
申请号：US09411786
申请日：1999-10-01
IPC分类号： G06F945
CPC分类号： G06F11/3648
摘要： A computer system, comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system; each watchpoint in the set of watchpoints comprising a programmable precondition register and a programmable action register, a set of latches, and selection circuitry that selects one latch in the set of latches to couple an output of an action register to an input of the selected latch.
摘要翻译： 一种计算机系统，包括至少一个中央处理单元和耦合到所述至少一个中央处理单元的存储单元，在所述计算机系统中定义的一组观察点; 观察点组中的每个观察点包括可编程前置条件寄存器和可编程动作寄存器，一组锁存器和选择电路，其选择锁存器组中的一个锁存器以将动作寄存器的输出耦合到所选择的锁存器的输入 。
-
-
-
-
-
-
-
-
-
搜索结果
32 条记录 (耗时 0.044 秒)
