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公开(公告)号：US20060176982A1
公开(公告)日：2006-08-10
申请号：US11054060
申请日：2005-02-09
申请人： David Berman , Evangelos Eleftherion , Robert Hutchins , Glen Jaquette , Constantin Melas , Sedat Oelcer
发明人： David Berman , Evangelos Eleftherion , Robert Hutchins , Glen Jaquette , Constantin Melas , Sedat Oelcer
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10296 , G11B2220/2516
摘要： An apparatus, system, and method are disclosed for asymmetric maximum likelihood detection. An initialization module initializes a plurality of branch metrics and a plurality of path memories. A coefficient module calculates a plurality of coefficients. A computation module calculates a first and second specified likelihood function. A selection module calculates a third specified branch metric as the maximum of the first and second specified likelihood functions. A path metrics module calculates a third specified path memory from a first and second specified path memory. A results module identifies a data output value from one or more path memories.
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公开(公告)号：US20050144534A1
公开(公告)日：2005-06-30
申请号：US10737563
申请日：2003-12-15
申请人： Robert Hutchins , Glen Jaquette , David Berman , Constantin Melas
发明人： Robert Hutchins , Glen Jaquette , David Berman , Constantin Melas
IPC分类号： G06F11/00
CPC分类号： G11B20/10009
摘要： Disclosed is a technique for updating a read-detect channel. A signal is processed in a read-detect channel that has one or more programmable registers. While signals continue to be processed by the read-detect channel, it is determined with a channel auxiliary processor whether to dynamically replace values of the one or more programmable registers. When it is determined that values of the one or more programmable registers are to be replaced, a channel auxiliary processor determines values for the one or more programmable registers and replaces existing values for the one or more programmable registers with the determined values. Also disclosed is a technique in which the determined values for the one or more programmable registers are determined using a sample of the signal. Moreover, disclosed is a technique in which the channel auxiliary processor receives error information for the signal and determines whether to replace values of the one or more programmable registers with stored values based on the error information.
摘要翻译： 公开了一种更新读取检测通道的技术。 在具有一个或多个可编程寄存器的读取检测通道中处理信号。 当信号继续由读取检测通道处理时，用信道辅助处理器确定是否动态地替换一个或多个可编程寄存器的值。 当确定要替换一个或多个可编程寄存器的值时，信道辅助处理器确定一个或多个可编程寄存器的值，并用所确定的值替换一个或多个可编程寄存器的现有值。 还公开了一种技术，其中使用信号的采样来确定一个或多个可编程寄存器的确定值。 此外，公开了一种技术，其中信道辅助处理器接收信号的错误信息，并且基于错误信息确定是否用存储的值替换一个或多个可编程寄存器的值。
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公开(公告)号：US20060119969A1
公开(公告)日：2006-06-08
申请号：US11003283
申请日：2004-12-03
摘要： A read channel equalizer of a magnetic tape drive which equalizes digitally sampled magnetic signals detected by a read head is dynamically adapted. A detector of equalizer dynamic adaptation logic compares equalizer output signals to desired values that are based on the decoding scheme (such as +2, 0 and −2 for PR4) to sense equalizer output signals that are offset from at least one desired value, and signals the fact of each offset and its polarity as amplitude independent error signals. The signaled sensed amplitude independent error signals are fed back to adjustable taps of the equalizer. The simplified error signals thus avoid complex calculations of waveform errors, such as least mean square calculations. The error signals may be weighted and may be adjusted to align synchronously provided error signals with asynchronous taps of the equalizer.
摘要翻译： 磁头驱动器的读取通道均衡器，其均衡由读取头检测到的数字采样磁信号。 均衡器动态适配逻辑的检测器将均衡器输出信号与基于解码方案（例如PR4的+2,0和-2）的期望值进行比较，以感测与至少一个期望值偏移的均衡器输出信号，以及 将每个偏移及其极性的事实表示为与振幅无关的误差信号。 信号感知的与振幅无关的误差信号反馈到均衡器的可调节抽头。 因此，简化的误差信号避免了波形误差的复杂计算，例如最小均方根计算。 误差信号可以被加权并且可以被调整以使同步提供的误差信号与均衡器的异步抽头对齐。
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4.发明申请Using at least one servo channel to provide timing recovery and timing information to data channels 失效使用至少一个伺服通道来向数据通道提供定时恢复和定时信息公开(公告)号：US20070177292A1
公开(公告)日：2007-08-02
申请号：US11346391
申请日：2006-02-01
申请人： Nhan Bui , Giovanni Cherubini , Evangelos Eleftheriou , Robert Hutchins , Glen Jaquette , Jens Jelitto , Sedat Oelcer , Mark Taylor
发明人： Nhan Bui , Giovanni Cherubini , Evangelos Eleftheriou , Robert Hutchins , Glen Jaquette , Jens Jelitto , Sedat Oelcer , Mark Taylor
IPC分类号： G11B5/09
CPC分类号： G11B27/36 , G11B20/10037 , G11B20/10046 , G11B20/10055 , G11B20/10212 , G11B20/10259 , G11B20/1403 , G11B20/1876 , G11B27/10 , G11B2020/10592 , G11B2220/90 , G11B2220/95
摘要： Provided is a read channel, storage drive, and method to process signals read from a storage medium. At least one data channel including an interpolator and equalizer and a servo channel includes an interpolator. A timing recovery function processes a timing error from the interpolator in the servo channel to calculate interpolation timing information used by the interpolator to interpolate a servo channel signal. A path is coupled to the timing recovery function and the interpolator in the at least one data channel to communicate the interpolation timing information to the interpolator in the at least one data channel. The interpolator in the at least one data channel is configured to use the interpolation timing information to interpolate an asynchronous data channel signal.
摘要翻译： 提供了一种用于处理从存储介质读取的信号的读通道，存储驱动器和方法。 包括内插器和均衡器和伺服信道的至少一个数据信道包括内插器。 定时恢复功能处理来自伺服信道中的内插器的定时误差，以计算内插器使用的内插定时信息来内插伺服信道信号。 路径耦合到至少一个数据信道中的定时恢复功能和内插器，以将内插定时信息传送到至少一个数据信道中的内插器。 所述至少一个数据信道中的内插器被配置为使用内插定时信息来内插异步数据信道信号。
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5.发明申请Magnetic tape read channel signal values developed employing intermediate bits of the path memory of a PRML viterbi detector 失效使用PRML维特比检测器的路径存储器的中间位开发的磁带读取通道信号值公开(公告)号：US20060119964A1
公开(公告)日：2006-06-08
申请号：US11003316
申请日：2004-12-03
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/10074 , G11B20/10296 , G11B2220/90
摘要： Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence.
摘要翻译： 使用PRML维特比检测器的路径存储器的中间位来开发磁带读取通道信号值。 识别逻辑根据PRML维特比检测器的路径度量来识别PRML维特比检测器的最可能的路径存储状态。 获得所识别的最可能的路径存储器状态的中间比特序列，从位于PRML维特比检测器的输出和输入之间的路径存储器的起始点延伸的中间比特序列。 确定对应于获得的中间位序列的采样值。
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6.发明申请公开(公告)号：US20070047121A1
公开(公告)日：2007-03-01
申请号：US11213127
申请日：2005-08-26
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10046 , G11B20/10055
摘要： A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.
摘要翻译： 公开了使用该读通道的读通道和方法。 读通道包括模数转换器，其以固定速率异步采样通过读取数据轨道形成的模拟信号，其中数据轨道以符号速率写入数据存储介质，并且与模数转换器互连的内插器 转换器。 读通道还包括分数间隔的均衡器，其中内插器以内插速率向分数间隔的均衡器提供内插信号，其中该内插速率大于符号率。 分数间隔均衡器形成同步均衡信号。 读通道还包括与分数间隔均衡器互连的增益控制模块，以及与增益控制模块互连的序列检测器。
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公开(公告)号：US20060082915A1
公开(公告)日：2006-04-20
申请号：US10966531
申请日：2004-10-15
IPC分类号： G11B5/02
CPC分类号： H03M1/1042 , G11B20/10 , G11B2220/90
摘要： An apparatus, system, and method are disclosed for mitigating signal asymmetry. An analog to digital converter samples an analog signal from a read head and converts the sample to a digital input signal. The digital input signal addresses a look-up module, and the look-up module outputs a modified digital signal. The modified digital signal value is a specified function of the digital input signal value, wherein the specified function is configured to mitigate the asymmetry of the digital input signal. The modified digital signal value may be periodically recalculated to adjust for read head wear.
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公开(公告)号：US20070047127A1
公开(公告)日：2007-03-01
申请号：US11215409
申请日：2005-08-30
IPC分类号： G11B5/035
CPC分类号： G11B5/035 , G11B20/10046 , G11B20/10212 , G11B20/1201
摘要： Provided is a read channel incorporated in a storage device to process signals read from a storage medium. The read channel includes an equalizer equalizing input read signals to produce equalizer output signals. A detector senses an adjusted equalizer output signal to determine an output value comprising data represented by the input read signals. An equalizer adaptor receives the output value from the detector to determine a first error signal used to adjust the equalizer operations. A component adjusts the equalizer output signals being transmitted to the detector, wherein the component is adjusted by a second error signal calculated from the output value from the detector, wherein the first and second error signals are different.
摘要翻译： 提供了一种结合在存储装置中以读取从存储介质读取的信号的读通道。 读通道包括均衡器均衡输入读信号以产生均衡器输出信号。 检测器感测调整的均衡器输出信号以确定包括由输入读取信号表示的数据的输出值。 均衡器适配器从检测器接收输出值以确定用于调整均衡器操作的第一误差信号。 一个分量调整正被发送到检测器的均衡器输出信号，其中通过从检测器的输出值计算的第二误差信号调整分量，其中第一和第二误差信号是不同的。
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9.发明申请Method for a cyclic dibit response estimation in a media system using a data set separator sequence 失效在使用数据集分隔符序列的媒体系统中进行循环双位响应估计的方法公开(公告)号：US20060250719A1
公开(公告)日：2006-11-09
申请号：US11122680
申请日：2005-05-05
IPC分类号： G11B5/09
CPC分类号： G11B20/10 , G11B20/10009 , G11B20/10046
摘要： A dibit response estimation generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a cyclic dibit response vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS readback sequence and a filtering of the DSS sequence based on the cyclic dibit response vector. An unacceptable error signal indicates a need to adjust the cyclic dibit response vector to yield an acceptable comparison of the DSS readback sequence and the filtering of the DSS sequence based on the cyclic dibit response vector.
摘要翻译： 双向响应估计生成器接收DSS序列和DSS回读序列，DSS序列是通过读取通道的DSS序列的信道处理的函数。 发生器产生作为DSS序列和DSS回读序列的函数的循环双位响应向量。 发生器还根据DSS回读序列的比较和基于循环双位响应向量的DSS序列的滤波产生误差信号。 不可接受的误差信号表示需要调整循环双位响应向量，以产生DSS回读序列的可接受比较和基于循环双位响应向量的DSS序列的过滤。
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10.发明申请Apparatus, system, and method for adaptive asynchronous equalization using leakage 有权使用泄漏进行自适应异步均衡的装置，系统和方法公开(公告)号：US20070098061A1
公开(公告)日：2007-05-03
申请号：US11263189
申请日：2005-10-31
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10175 , G11B20/10481 , H04L25/03019 , H04L2025/03484 , H04L2025/03681
摘要： An apparatus, system, and method are disclosed for adaptive asynchronous equalization using leakage. An equalizer sums products of a plurality of tap signals from a delay line sampling a read signal and a plurality of corresponding tap coefficients to form an equalized signal in an asynchronous time domain having a first sampling rate. A leaky function module calculates a leaky function for each tap coefficient in the asynchronous time domain. An adaptation module adapts each of the tap coefficients as the leaky function for each tap coefficient summed with a signal-dependent updating function for each tap coefficient.
摘要翻译： 公开了一种使用泄漏进行自适应异步均衡的装置，系统和方法。 均衡器对来自对读取信号进行采样的延迟线和多个对应抽头系数的多个抽头信号的乘积相加，以在具有第一采样率的异步时域中形成均衡信号。 泄漏功能模块计算异步时域中每个抽头系数的泄漏函数。 适配模块将每个抽头系数适配为每个抽头系数的泄漏函数，用于针对每个抽头系数的与信号相关的更新函数相加。
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