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1.发明申请FLASH ARRAY BUILT IN SELF TEST ENGINE WITH TRACE ARRAY AND FLASH METRIC REPORTING 有权闪存阵列用自动测试引擎内置跟踪阵列和闪存公制报告公开(公告)号：US20130151914A1
公开(公告)日：2013-06-13
申请号：US13314657
申请日：2011-12-08
CPC分类号： G06F11/1068 , G11C16/00 , G11C29/16
摘要： A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.
摘要翻译： 为闪存阵列测试引擎提供了一种机制。 闪存阵列测试引擎包括一个电路。 电路被配置为在测试模式下生成测试工作负载，用于测试闪存器件阵列，其中每个测试工作负载包括要发送到闪存器件阵列的特定地址，数据和命令模式。 该电路被配置为相对于不属于测试模式的一般系统工作负载，以加速的速度通过测试工作负载加速闪存器件阵列中的磨损。 电路被配置为改变闪存器件阵列的条件范围，以确定每个条件是否通过或失败，并存储闪存器件阵列的故障数据和相应的故障数据地址信息。
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2.发明授权Flash array built in self test engine with trace array and flash metric reporting 有权闪存阵列内置自检引擎，具有跟踪数组和闪存指标报告公开(公告)号：US08627158B2
公开(公告)日：2014-01-07
申请号：US13314657
申请日：2011-12-08
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C16/00 , G11C29/16
摘要： A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.
摘要翻译： 为闪存阵列测试引擎提供了一种机制。 闪存阵列测试引擎包括一个电路。 电路被配置为在测试模式下生成测试工作负载，用于测试闪存器件阵列，其中每个测试工作负载包括要发送到闪存器件阵列的特定地址，数据和命令模式。 该电路被配置为相对于不属于测试模式的一般系统工作负载，以加速的速度通过测试工作负载加速闪存器件阵列中的磨损。 电路被配置为改变闪存器件阵列的条件范围，以确定每个条件是否通过或失败，并存储闪存器件阵列的故障数据和相应的故障数据地址信息。
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