公开(公告)号：US11776618B2

公开(公告)日：2023-10-03

申请号：US17520749

申请日：2021-11-08

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Po-Hao Tseng

IPC分类号： G11C15/00 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/408 ,  G11C16/00 ,  G11C15/04

CPC分类号： G11C11/4093 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  G11C15/046 ,  G11C16/00 ,  G11C15/00

摘要： The present invention discloses a memory device and operation method thereof. The operation method comprises: programming a plurality of first strings of a plurality of string pairs representing a finite state machine (FSM) to an in-memory-searching (IMS) array of a memory device; programming a plurality of second strings of the string pairs to a working memory of the memory device; and programming a string representing a starting state of the FSM to a buffer of the memory device.

公开(公告)号：US11762788B2

公开(公告)日：2023-09-19

申请号：US17114478

申请日：2020-12-07

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C8/18 ,  G11C16/00 ,  G11C29/02 ,  G11C7/20 ,  G11C8/12 ,  G11C29/04

CPC分类号： G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  H05K999/99 ,  G11C7/109 ,  G11C7/20 ,  G11C8/12 ,  G11C2029/0407

摘要： A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

公开(公告)号：US20180358360A1

公开(公告)日：2018-12-13

申请号：US16106643

申请日：2018-08-21

申请人： Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： H01L27/108 ,  G11C11/404 ,  G11C11/407 ,  H01L29/06 ,  G11C16/00 ,  H01L29/78 ,  G11C16/04

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C11/407 ,  G11C16/00 ,  G11C16/0416 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/7841 ,  H01L29/7885

摘要： A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

公开(公告)号：US20180239721A1

公开(公告)日：2018-08-23

申请号：US15959354

申请日：2018-04-23

申请人： Toshiba Memory Corporation

发明人： Yoshikazu TAKEYAMA ,  Masaru KOYANAGI ,  Akio SUGAHARA

IPC分类号： G06F13/16 ,  G11C16/08 ,  G06F13/36 ,  G06F13/40

CPC分类号： G06F13/1668 ,  G06F13/36 ,  G06F13/4068 ,  G11C7/1084 ,  G11C8/12 ,  G11C14/0018 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/0407 ,  G11C2029/0409

摘要： According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

公开(公告)号：US20180196612A1

公开(公告)日：2018-07-12

申请号：US15860648

申请日：2018-01-02

申请人： Intel Corporation

发明人： Kiran Pangal ,  Ravi J. Kumar

IPC分类号： G06F3/06 ,  G11C29/52 ,  G11C29/50 ,  G11C29/02 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C11/56 ,  G06F11/20 ,  G06F11/10 ,  G11C16/00 ,  G11C29/04

CPC分类号： G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

摘要： Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

公开(公告)号：US10014062B2

公开(公告)日：2018-07-03

申请号：US15084943

申请日：2016-03-30

申请人： MICRON TECHNOLOGY, INC.

发明人： Violante Moschiano ,  Giovanni Santin

IPC分类号： G11C16/34 ,  G11C11/56 ,  G11C16/06 ,  G11C16/24 ,  G11C16/10 ,  G11C16/00 ,  G11C29/04

CPC分类号： G11C16/3436 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/00 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C16/3481 ,  G11C2029/0409

摘要： Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank of a byte of information of a programming operation of the memory device, and a second buffer selectively connected to the array of memory cells and corresponding to the particular bit rank of a different byte of information of the programming operation of the memory device, wherein an output of the first buffer and an output of the second buffer are connected in parallel to a common line, as well as methods of their operation to indicate a pass/fail condition of the programming operation.

公开(公告)号：US20180136872A1

公开(公告)日：2018-05-17

申请号：US15459675

申请日：2017-03-15

申请人： Kneron, Inc.

发明人： Yuan DU ,  Li DU ,  Yi-Lei LI ,  Yen-Cheng KUAN ,  Chun-Chen LIU

IPC分类号： G06F3/06 ,  G06F17/15

CPC分类号： G06F17/153 ,  G06F5/00 ,  G06F12/02 ,  G06F17/15 ,  G06N3/0454 ,  G06N3/063 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/54 ,  G11C16/00 ,  Y04S10/54

摘要： A buffer device includes input lines, an input buffer unit and a remapping unit. The input lines are coupled to a memory and configured to be inputted with data from the memory in a current clock. The input buffer unit is coupled to the input lines and configured to buffer one part of the inputted data and output the part of the inputted data in a later clock. The remapping unit is coupled to the input lines and the input buffer unit, and configured to generate remap data for a convolution operation according to the data on the input lines and the output of the input buffer unit in the current clock. A convolution operation method for a data stream is also disclosed.

公开(公告)号：US09946472B2

公开(公告)日：2018-04-17

申请号：US15048500

申请日：2016-02-19

申请人： Hitachi, Ltd.

发明人： Akifumi Suzuki ,  Takashi Tsunehiro

IPC分类号： G11C29/02 ,  G11C16/34 ,  G11C16/00 ,  G06F3/06

CPC分类号： G06F3/0616 ,  G06F3/0629 ,  G06F3/0679 ,  G11C16/00 ,  G11C16/3431 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

摘要： A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

公开(公告)号：US20180019022A1

公开(公告)日：2018-01-18

申请号：US15212648

申请日：2016-07-18

申请人： International Business Machines Corporation

发明人： Jeffrey W. Christensen ,  Phillip E. Christensen ,  Robert S. Miller ,  Matthew S. Reuter ,  Antoine G. Sater

IPC分类号： G11C29/38 ,  G11C29/44 ,  G11C29/36

CPC分类号： G11C29/38 ,  G11C16/00 ,  G11C29/36 ,  G11C29/44

摘要： A computer-implemented method includes receiving probability distribution function (PDF) data corresponding to bit-error-rate (BER) data for each of a plurality of data blocks within a qualified set of NVRAMS, collecting non-exhaustive bit-error-rate data for each of the data blocks on a tested NVRAM to produce non-exhaustive test data for each of the data blocks, determining a plurality of stable data blocks on the tested NVRAM based on the non-exhaustive test data and the probability distribution function data for each of the data blocks, determining, from the non-exhaustive test data, an inferior data block for the stable data blocks on the tested NVRAM, collecting exhaustive bit-error-rate data on the inferior data block to produce exhaustive test data for the tested NVRAM, and routing the tested NVRAM according to the exhaustive test data. A corresponding computer program product and computer system are also disclosed herein.

公开(公告)号：US09847139B2

公开(公告)日：2017-12-19

申请号：US13632294

申请日：2012-10-01

申请人： Seagate Technology LLC

发明人： Zhengang Chen ,  Erich F. Haratsch

IPC分类号： G06F19/00 ,  G11C29/02 ,  G11C16/00 ,  G11C29/04

CPC分类号： G11C29/021 ,  G11C16/00 ,  G11C29/028 ,  G11C2029/0409

摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the statistics of one or more outliers of the units in the region exceeds a corresponding threshold and (iii) track the parameters of the outlier units separately from the parameters of the region in response to exceeding the corresponding threshold. The parameters generally control one or more reference voltages used to read the data from the region.