公开(公告)号：US4821170A

公开(公告)日：1989-04-11

申请号：US40513

申请日：1987-04-17

申请人： David L. Bernick ,  Kenneth K. Chan ,  Wing M. Chan ,  Yie-Fong Dan ,  Duc M. Hoang ,  Zubair Hussain ,  Geoffrey I. Iswandhi ,  James E. Korpi ,  Martin W. Sanner ,  Jay A. Zwagerman ,  Steven G. Silverman ,  James E. Smith

发明人： David L. Bernick ,  Kenneth K. Chan ,  Wing M. Chan ,  Yie-Fong Dan ,  Duc M. Hoang ,  Zubair Hussain ,  Geoffrey I. Iswandhi ,  James E. Korpi ,  Martin W. Sanner ,  Jay A. Zwagerman ,  Steven G. Silverman ,  James E. Smith

IPC分类号： G06F11/18 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40 ,  G06F15/16

CPC分类号： G06F13/28 ,  G06F13/122 ,  G06F13/4022 ,  G06F11/10

摘要： In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

公开(公告)号：US4821295A

公开(公告)日：1989-04-11

申请号：US126997

申请日：1987-11-30

申请人： Martin W. Sanner

发明人： Martin W. Sanner

IPC分类号： G06F1/12 ,  H03K5/00 ,  H03K5/135 ,  H04L7/02

CPC分类号： H03K5/135

摘要： A method, and apparatus to implement that method, for synchronizing an incoming signal to the transitions of a digital clock signal in the form of a periodic pulse train. The apparatus includes a first circuit pair of flip-flops arranged to sample and store the state of the input signal on either the positive and negative transitions of the periodic pulse train, an OR gate producing a signal indicative of the stored content of the first circuit, and a third circuit that samples and stores the first signal at each transition of the periodic pulse train to produce therefrom a representation of the input signal synchronized to one of the transitions of the pulse train.

公开(公告)号：US4845712A

公开(公告)日：1989-07-04

申请号：US126525

申请日：1987-11-30

申请人： Martin W. Sanner ,  Seema Chandra

发明人： Martin W. Sanner ,  Seema Chandra

IPC分类号： G06F11/30 ,  G06F11/00 ,  G06F11/26 ,  G06F11/28 ,  G06F13/00

CPC分类号： G06F11/261 ,  G06F11/28

摘要： Checking method and apparatus for monitoring the proper operation of a state machine of the type operable to produce control signals that in turn, cause other digital apparatus to produce responsive signals. Part of the checker apparatus, in effect, emulates the digital apparatus, receiving the control signals to produce therefrom emulated response signals that, when compared to the control signals, provide an indication of correct operation of the state machine means and associated circuitry.

公开(公告)号：US4872172A

公开(公告)日：1989-10-03

申请号：US126806

申请日：1987-11-30

申请人： Martin W. Sanner

发明人： Martin W. Sanner

IPC分类号： G06F11/10

CPC分类号： G06F11/10

摘要： A parity regeneration and self-check technique is used for detecting and locating errors in data communicated to, through, and from a digital subsystem. The invention utilizes a parity check associated with a data input of the subsystem, regenerating parity for data communicated from an output of the subsystem, checking the regenerated parity and comparing that check with other checks.

公开(公告)号：US4879718A

公开(公告)日：1989-11-07

申请号：US126998

申请日：1987-11-30

申请人： Martin W. Sanner

发明人： Martin W. Sanner

IPC分类号： G06F11/22 ,  G01R31/3185

CPC分类号： G01R31/318552

摘要： Apparatus is disclosed for forming scan data path subchains from the elemental memory units of a digital system, and interconnecting the scan data path subchains to form an extended serial shift register for scan testing. The method and apparatus for forming the interconnections ensures that data is passed from one subchain to another without data being lost due to clocking irregularities.

公开(公告)号：US4876701A

公开(公告)日：1989-10-24

申请号：US126971

申请日：1987-11-30

申请人： Martin W. Sanner

发明人： Martin W. Sanner

IPC分类号： G06F1/04 ,  G06F11/00 ,  H03K5/00 ,  H04L1/24 ,  H04L7/00

CPC分类号： H04L1/246

摘要： A method, and apparatus implementing that method, for monitoring a synchronization circuit to ensure proper operation thereof. The synchronization circuit is of the type that receives asynchronously occurring input pulses to produce therefrom representations of the received input pulses, having state transitions synchronized to the state transitions of a periodic clock signal. The invention also receives the input pulses and the synchronized representation of those pulses, to ensure that for every input pulse there is provided a synchronized pulse by the synchronization circuit.