公开(公告)号：US06389509B1

公开(公告)日：2002-05-14

申请号：US08866426

申请日：1997-05-30

申请人： Leo Berenguel ,  James E. Korpi ,  Conne Lin

发明人： Leo Berenguel ,  James E. Korpi ,  Conne Lin

IPC分类号： G06F1208

CPC分类号： G06F3/0613 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0677 ,  G06F12/0866 ,  G06F2212/312

摘要： A memory cache device for a CD-ROM for use with a host computer capable of initially filling a clone area of the hard disk with data from the compact disc using a sequential striped fill process for copying a plurality of blocks of data from the compact disc to the hard disk, the process comprising the steps of: accessing a first block of data of a sequence of data blocks from the compact disc and copying the first block onto the hard disk, accessing a second block of data in the sequence of data blocks from the compact disc and not copying the second block to the hard disk, and accessing a third block of data in the sequence of data blocks from the compact disc and copying the third block onto the hard disk, the fill process continuing until the entire capacity of the hard disk devoted to cloning the compact disk is full, while leaving sufficient area for storage of blocks not initially copied in the fill process.

摘要翻译： 一种用于与主计算机一起使用的CD-ROM的存储器高速缓存设备，其能够使用用于从光盘复制多个数据块的顺序条带填充处理来初始填充来自光盘的数据的硬盘的克隆区域 该过程包括以下步骤：从光盘访问数据块序列的第一数据块并将第一块复制到硬盘上，访问数据块序列中的第二数据块 从光盘中并不将第二块复制到硬盘，并且从光盘访问数据块序列中的第三块数据，并将第三块复制到硬盘上，则填充过程持续到整个容量 用于克隆光盘的硬盘已满，同时留下足够的存储块，最初不会在填充过程中复制。

公开(公告)号：US5884093A

公开(公告)日：1999-03-16

申请号：US512860

申请日：1995-08-07

申请人： Leo P. Berenguel ,  James E. Korpi ,  Connie Lin

发明人： Leo P. Berenguel ,  James E. Korpi ,  Connie Lin

IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F3/0613 ,  G06F12/0866 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0677 ,  G06F2212/312

摘要： A controller system for a CD-ROM drive or other slow access device such as a magneto-optical device using a conventional hard disk drive as a cache memory. In some embodiments, the hard disk cache is partitioned to use a portion thereof to clone the most often used data blocks on the CD-ROM disk such as the directory/file allocation table, while the balance of the hard disk is used to cache some or all of the balance of the CD-ROM disk using conventional cache memory least recently used rules. Three bus controllers for the host computer, CD-ROM drive and the hard disk cache are controlled by a microprocessor which runs a control program that implements the cloning and cache rules. The three bus controllers are connected by a DMA bus for faster transfer of data. The microprocessor controls the directions of the DMA transfers by data written to a control register.

摘要翻译： 用于CD-ROM驱动器或其他慢速存取装置的控制器系统，例如使用常规硬盘驱动器作为高速缓冲存储器的磁光设备。 在一些实施例中，硬盘高速缓存被分区以使用其部分来克隆CD-ROM盘上最常使用的数据块，例如目录/文件分配表，而硬盘的平衡用于缓存一些 或使用常规高速缓存存储器最少使用的规则的CD-ROM磁盘的所有平衡。 用于主机，CD-ROM驱动器和硬盘缓存的三个总线控制器由运行执行克隆和高速缓存规则的控制程序的微处理器控制。 三总线控制器通过DMA总线连接，从而更快地传输数据。 微处理器通过写入控制寄存器的数据来控制DMA传输的方向。

公开(公告)号：US4864291A

公开(公告)日：1989-09-05

申请号：US209672

申请日：1988-06-21

申请人： James E. Korpi

发明人： James E. Korpi

IPC分类号： G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  H04L12/413

CPC分类号： G06F13/4226 ,  G06F13/4027 ,  H04L12/4135

摘要： A converter for coupling a single-ended and a differential SCSI bus that facilitates the use of the ARB, SELECTION, and RESELECTION phases of the SCSI protocol.

公开(公告)号：US4821170A

公开(公告)日：1989-04-11

申请号：US40513

申请日：1987-04-17

申请人： David L. Bernick ,  Kenneth K. Chan ,  Wing M. Chan ,  Yie-Fong Dan ,  Duc M. Hoang ,  Zubair Hussain ,  Geoffrey I. Iswandhi ,  James E. Korpi ,  Martin W. Sanner ,  Jay A. Zwagerman ,  Steven G. Silverman ,  James E. Smith

发明人： David L. Bernick ,  Kenneth K. Chan ,  Wing M. Chan ,  Yie-Fong Dan ,  Duc M. Hoang ,  Zubair Hussain ,  Geoffrey I. Iswandhi ,  James E. Korpi ,  Martin W. Sanner ,  Jay A. Zwagerman ,  Steven G. Silverman ,  James E. Smith

IPC分类号： G06F11/18 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40 ,  G06F15/16

CPC分类号： G06F13/28 ,  G06F13/122 ,  G06F13/4022 ,  G06F11/10

摘要： In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.