公开(公告)号：US5553263A

公开(公告)日：1996-09-03

申请号：US92835

申请日：1993-07-16

申请人： David M. Kalish ,  Saul Barajas ,  Paul B. Ricci

发明人： David M. Kalish ,  Saul Barajas ,  Paul B. Ricci

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F12/08 ,  G06F12/02 ,  G06F13/00

CPC分类号： G06F11/2017 ,  G06F12/0851

摘要： A processor cache memory system utilizes separate cache controllers for independently managing even and odd input address requests with the even and odd address requests being mapped into the respective controllers. Each cache controller includes tag RAM for storing address tags, including a field for storing the least significant address bit, so that the stored tags distinguish between the odd and even addresses. Upon failure of a cache controller, both the even and odd addresses are directed to the operational controller and the stored least significant bit address tag distinguishes between the odd and even input addresses to appropriately generate HIT/MISS signals. The controllers include block address counter logic for generating respective even and odd invalidation addresses for simultaneously performing invalidation cycles thereon when both controllers are operational. When a controller fails, the block address counter logic generates both even and odd block invalidation addresses in the operational controller.

摘要翻译： 处理器高速缓冲存储器系统利用单独的高速缓存控制器来独立地管理偶数和奇数输入地址请求，偶数和奇数地址请求被映射到相应的控制器中。 每个高速缓存控制器包括用于存储地址标签的标签RAM，包括用于存储最低有效地址位的字段，使得存储的标签区分奇数和偶数地址。 在高速缓存控制器发生故障时，偶数和奇数地址都被定向到操作控制器，并且所存储的最低有效位地址标签区分奇数和偶数输入地址以适当地生成HIT / MISS信号。 控制器包括块地址计数器逻辑，用于当两个控制器都可操作时，产生用于同时执行无效循环的相应偶数和奇数无效地址。 当控制器出现故障时，块地址计数器逻辑在运算控制器中产生偶数和奇数块无效地址。

公开(公告)号：US5553259A

公开(公告)日：1996-09-03

申请号：US547577

申请日：1995-10-24

申请人： David M. Kalish ,  Saul Barajas ,  Paul B. Ricci

发明人： David M. Kalish ,  Saul Barajas ,  Paul B. Ricci

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F12/08

CPC分类号： G06F11/167 ,  G06F12/0851 ,  G06F11/1008

摘要： A method and implementation is supplied for the synchronous loading and integrity checking of registers located in two different integrated circuit chips. Thus in a computer system having cache memory where the cache memory is sliced into two portions, one of which holds even addresses and the other of which holds odd addresses, there is provided two individual chips each of which has a program word address register which is loaded at the exact same period of time and which is additionally incremented in both cases at the exact same period of time. Further means are provided for checking the integrity of the program word address registers in the first slice and the second slice of the cache in order to insure that they are coherent, or if not coherent, then a disable signal will prevent usage of the address data involved.

摘要翻译： 提供了一种用于同步加载和完整性检查位于两个不同集成电路芯片中的寄存器的方法和实现。 因此，在具有高速缓存存储器的计算机系统中，其中高速缓冲存储器被分成两部分，其中一个保持偶数地址，另一个保持奇数地址，提供两个单独的芯片，每个芯片具有一个程序字地址寄存器， 在完全相同的时间段内加载，并且在完全相同的时间段内在两种情况下另外增加。 提供另外的装置用于检查第一切片和高速缓存的第二切片中的程序字地址寄存器的完整性，以确保它们是相干的，或者如果不相干，则禁用信号将阻止使用地址数据 涉及。

公开(公告)号：US5506967A

公开(公告)日：1996-04-09

申请号：US78361

申请日：1993-06-15

申请人： Saul Barajas ,  David M. Kalish ,  Bruce E. Whittaker

发明人： Saul Barajas ,  David M. Kalish ,  Bruce E. Whittaker

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0808 ,  G06F12/0831

摘要： In a time-shared bus computer system with processors having cache memories, an adjustable invalidation queue for use in the cache memories. The invalidation queue has adjustable upper and lower limit positions that define when the queue is logically full and logically empty, respectively. The queue is flushed down to the lower limit when the contents of the queue attain the upper limit. During the queue flushing operation, WRITE requests on the bus are RETRYed. The computer maintenance system sets the upper and lower limits at system initialization time to optimize system performance under maximum bus traffic conditions.

摘要翻译： 在具有处理器的具有高速缓存存储器的时分共享总线计算机系统中，可用于高速缓冲存储器的可调节无效队列。 无效队列具有可调节的上限和下限位置，可以分别定义队列在逻辑上完全和逻辑上为空。 当队列的内容达到上限时，队列被刷新到下限。 在队列刷新操作期间，总线上的WRITE请求被复原。 计算机维护系统在系统初始化时间设置上限和下限，以在最大总线流量条件下优化系统性能。

公开(公告)号：US5689680A

公开(公告)日：1997-11-18

申请号：US92408

申请日：1993-07-15

申请人： Bruce E. Whittaker ,  David M. Kalish ,  Saul Barajas

发明人： Bruce E. Whittaker ,  David M. Kalish ,  Saul Barajas

IPC分类号： G06F12/08 ,  G06F12/02 ,  G06F13/00

CPC分类号： G06F12/0808 ,  G06F12/0831

摘要： A "bit-sliced" construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values. Preferably, one half-module handles ZERO least-significant bits and the other handles ONE least-significant bits. Processor operations and invalidation operations can be "overlapped", and even operate simultaneously.

摘要翻译： “位片”构建缓存模块指示双重TAG RAM结构和双无效队列，从而产生增强的性能：将TAG阵列放置在两个缓存阵列中的一个中，并允许每个只处理可能地址值的一半。 优选地，一个半模块处理ZERO最低有效位，而另一个处理一个最低有效位。 处理器操作和无效操作可以“重叠”，甚至可以同时操作。

公开(公告)号：US5561773A

公开(公告)日：1996-10-01

申请号：US56324

申请日：1993-04-30

申请人： David M. Kalish ,  Saul Barajas ,  Bruce E. Whittaker

发明人： David M. Kalish ,  Saul Barajas ,  Bruce E. Whittaker

IPC分类号： H03K19/173 ,  G06F11/00 ,  G06F7/38 ,  H01J3/00

CPC分类号： H03K19/1732

摘要： A system and circuitry is provided by which certain selected embedded pins of an integrated circuit gate array may be provided with dual functions, that is to say, they may act either as receivers of an externally sourced input signal or as transmitters of an internally generated output signal. Each selected input/output pin is controlled by an associated flip-flop residing in a chain of flip-flops so that an associated flip-flop will determine the condition of two buffer-drivers attached to each input/output pin. While the first buffer-driver is tri-stated (disabled), then the embedded pin operates as an input receiving function. When the first buffer-driver is enabled, the embedded I/O pin operates as the conveyer of an output signal from the internal output logic.

摘要翻译： 提供了一种系统和电路，通过该系统和电路可以提供集成电路门阵列的某些选定的嵌入式引脚具有双重功能，也就是说，它们可以作为外部来源输入信号的接收器，或作为内部产生的输出的发射器 信号。 每个选择的输入/输出引脚由驻留在触发器链中的相关联的触发器控制，使得相关联的触发器将确定连接到每个输入/输出引脚的两个缓冲器驱动器的状况。 当第一个缓冲驱动器为三态（禁用）时，嵌入式引脚作为输入接收功能。 当第一个缓冲驱动器被使能时，嵌入式I / O引脚作为来自内部输出逻辑的输出信号的输送器。

公开(公告)号：US5642486A

公开(公告)日：1997-06-24

申请号：US92433

申请日：1993-07-15

申请人： Bruce E. Whittaker ,  David M. Kalish ,  Saul Barajas

发明人： Bruce E. Whittaker ,  David M. Kalish ,  Saul Barajas

IPC分类号： G06F12/08

CPC分类号： G06F12/0808 ,  G06F12/0831 ,  Y10S707/99942

摘要： An Invalidation Queue (IQ) arrangement in a computer system having Main Memory and, Cache-Memory, with a pair of intermediate main-buses this IQ arrangement comprising: a pair of split IQ ASIC Arrays disposed between each Cache-Memory and the main-buses and being adapted to assure identical data in all identical memory addresses in different caches, and to "remember" write-operations along the buses and to execute invalidation sequences for any Cache-Memory unit as dictated by that Cache-Memory unit.

摘要翻译： 具有主存储器的计算机系统中的无效队列（IQ）布置，以及具有一对中间主总线的高速缓存存储器，该IQ布置包括：设置在每个高速缓存存储器和主存储器之间的一对分离IQ ASIC阵列， 总线，并且适于确保不同高速缓存中的所有相同存储器地址中的相同数据，并且沿着总线“记住”写入操作，并且执行由该高速缓存存储器单元所指示的任何高速缓存存储器单元的无效序列。

公开(公告)号：US5598551A

公开(公告)日：1997-01-28

申请号：US602259

申请日：1996-02-15

申请人： Saul Barajas ,  David M. Kalish ,  Bruce E. Whittaker ,  Keith S. Saldanha

发明人： Saul Barajas ,  David M. Kalish ,  Bruce E. Whittaker ,  Keith S. Saldanha

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/06

CPC分类号： G06F12/0835 ,  G06F12/0851 ,  G06F12/0891

摘要： By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both during a cache hit or a cache miss cycle, the present architecture and methodology permits a faster cycle of cache address invalidations when required and also permits a higher frequency of processor access to cache without the processor being completely locked out from cache memory access during heavy traffic and high level of cache invalidation conditions.

摘要翻译： 通过将高速缓存地址无效队列扩展为位片，用于保持奇无效地址甚至无效地址，并且还通过提供更有效的一系列转换周期来实现高速缓存命中或高速缓存未命中周期中的高速缓存地址无效，本架构和 方法允许在需要时缓存地址无效的循环更快，并且还允许更高频率的处理器访问高速缓存，而不会在繁忙的流量和高级别的高速缓存无效条件期间将处理器完全锁定在高速缓存存储器访问之外。