公开(公告)号：US07809007B2

公开(公告)日：2010-10-05

申请号：US10794067

申请日：2004-03-05

申请人： David Mayhew ,  Karl Meier ,  Nathan Dohm

发明人： David Mayhew ,  Karl Meier ,  Nathan Dohm

IPC分类号： H04L12/28 ,  H04L12/26 ,  H04J3/26

CPC分类号： H04L47/6205

摘要： The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

摘要翻译： 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外，它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息，它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时，输出队列中的数据包将发往拥塞路径，它将违规数据包置于拥塞流队列中，从而允许其他数据包发往 第一个输出端口继续传输。 以这种方式，解决了HOL阻塞问题，而不需要显着增加输出队列数量。

公开(公告)号：US20050195845A1

公开(公告)日：2005-09-08

申请号：US10794067

申请日：2004-03-05

申请人： David Mayhew ,  Karl Meier ,  Nathan Dohm

发明人： David Mayhew ,  Karl Meier ,  Nathan Dohm

IPC分类号： H04L12/28

CPC分类号： H04L47/6205

摘要： The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

摘要翻译： 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外，它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息，它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时，输出队列中的分组将发往拥塞路径，则将违规数据包置于拥塞流队列中，从而允许其他分组发往 第一个输出端口继续传输。 以这种方式，解决了HOL阻塞问题，而不需要显着增加输出队列数量。

公开(公告)号：US08531968B2

公开(公告)日：2013-09-10

申请号：US12872795

申请日：2010-08-31

申请人： David Mayhew ,  Karl Meier ,  Nathan Dohm

发明人： David Mayhew ,  Karl Meier ,  Nathan Dohm

IPC分类号： G01R31/08 ,  H04L12/28

CPC分类号： H04L47/6205

摘要： The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

摘要翻译： 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外，它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息，它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时，输出队列中的数据包将发往拥塞路径，它将违规数据包置于拥塞流队列中，从而允许其他数据包发往 第一个输出端口继续传输。 以这种方式，解决了HOL阻塞问题，而不需要显着增加输出队列数量。

公开(公告)号：US20110044175A1

公开(公告)日：2011-02-24

申请号：US12872795

申请日：2010-08-31

申请人： David Mayhew ,  Karl Meier ,  Nathan Dohm

发明人： David Mayhew ,  Karl Meier ,  Nathan Dohm

IPC分类号： H04L12/26

CPC分类号： H04L47/6205

摘要： The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

摘要翻译： 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外，它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息，它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时，输出队列中的数据包将发往拥塞路径，它将违规数据包置于拥塞流队列中，从而允许其他数据包发往 第一个输出端口继续传输。 以这种方式，解决了HOL阻塞问题，而不需要显着增加输出队列数量。

公开(公告)号：US07953024B2

公开(公告)日：2011-05-31

申请号：US12422909

申请日：2009-04-13

申请人： David Mayhew ,  Nathan Dohm

发明人： David Mayhew ,  Nathan Dohm

IPC分类号： H04J1/16 ,  H04L12/28

CPC分类号： H04L47/10 ,  H04L47/39

摘要： The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.

摘要翻译： 本发明提供了一种用于基于信用的流量控制的改进的架构。 简而言之，接收交换机内的存储器空间分为静态分配部分和动态分配部分两部分。 数据包首先被放置在动态分配的部分中，并且立即返回信用。 当动态分配的部分没有额外的空间时，分组然后被存储在静态分配给特定虚拟电路的存储器部分中。 当数据包从静态分配的内存部分中删除时，将返回积分。 这种情况允许在动态分配的存储器部分中存在可用空间时立即返回信用。 它还允许改进的总体存储器的共享，因为整个存储器的更多可以被提供给特定的虚拟电路。

公开(公告)号：US20060056292A1

公开(公告)日：2006-03-16

申请号：US10942203

申请日：2004-09-16

申请人： David Mayhew ,  Nathan Dohm

发明人： David Mayhew ,  Nathan Dohm

IPC分类号： H04L1/00

CPC分类号： H04L47/10 ,  H04L47/39

摘要： The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.

公开(公告)号：US20050080959A1

公开(公告)日：2005-04-14

申请号：US10945615

申请日：2004-09-21

申请人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

发明人： Lynne Brocco ,  Todd Comins ,  Nathan Dohm ,  David Mayhew ,  Carey McMaster

IPC分类号： G06F13/40 ,  H04L12/56 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F13/404 ,  H04L49/25 ,  H04L49/252

摘要： The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

公开(公告)号：US07451282B2

公开(公告)日：2008-11-11

申请号：US11076464

申请日：2005-03-09

申请人： Karl Meier ,  Nathan Dohm

发明人： Karl Meier ,  Nathan Dohm

IPC分类号： G06F12/00

CPC分类号： G11C7/1006

摘要： The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

摘要翻译： 本发明提供了一种用于接收高速顺序数据流的改进的装置和方法。 它利用存储存储器的概念来减少用于接收数据流的输入缓冲器所需的速度和大小。 这允许设备使用大的相对较慢的存储器元件，从而允许接收设备存储大量的顺序数据。 使用作为数据写入的控制信息被存储在存储体中，重排序元件随后能够以与接收流不同的顺序从多个存储体中检索数据元素， 并将数据流重组为原始序列。

公开(公告)号：US20060203570A1

公开(公告)日：2006-09-14

申请号：US11076464

申请日：2005-03-09

申请人： Karl Meier ,  Nathan Dohm

发明人： Karl Meier ,  Nathan Dohm

IPC分类号： G11C7/10

CPC分类号： G11C7/1006

摘要： The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

公开(公告)号：US07518996B2

公开(公告)日：2009-04-14

申请号：US10942203

申请日：2004-09-16

申请人： David Mayhew ,  Nathan Dohm

发明人： David Mayhew ,  Nathan Dohm

IPC分类号： H04J1/16 ,  H04L12/28

CPC分类号： H04L47/10 ,  H04L47/39

摘要： The invention provides an improved architecture for credit based flow control. Briefly, the memory space within the receiving switch is separated into two parts, a statically allocated portion and a dynamically allocated portion. Packets are first placed in the dynamically allocated portion, and the credits are returned immediately. When the dynamically allocated portion has no additional space, the packets are then stored in the memory portion statically allocated to the specific virtual circuit. Credits are returned when the packets are removed from the statically allocated memory portion. This scenario allows the immediate return of credits when there is space available in the dynamically allocated memory portion. It also allows improved sharing of the overall memory since more of the overall memory can be made available to a particular virtual circuit.

摘要翻译： 本发明提供了一种用于基于信用的流量控制的改进的架构。 简而言之，接收交换机内的存储器空间分为静态分配部分和动态分配部分两部分。 数据包首先被放置在动态分配的部分中，并且立即返回信用。 当动态分配的部分没有额外的空间时，分组然后被存储在静态分配给特定虚拟电路的存储器部分中。 当数据包从静态分配的内存部分中删除时，将返回积分。 这种情况允许在动态分配的存储器部分中存在可用空间时立即返回信用。 它还允许改进的总体存储器的共享，因为整个存储器的更多可以被提供给特定的虚拟电路。