Low cost implementation for a device utilizing look ahead congestion management
    1.
    发明授权
    Low cost implementation for a device utilizing look ahead congestion management 有权
    低成本实施的设备利用前瞻性拥塞管理

    公开(公告)号:US07809007B2

    公开(公告)日:2010-10-05

    申请号:US10794067

    申请日:2004-03-05

    IPC分类号: H04L12/28 H04L12/26 H04J3/26

    CPC分类号: H04L47/6205

    摘要: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

    摘要翻译: 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外,它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息,它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时,输出队列中的数据包将发往拥塞路径,它将违规数据包置于拥塞流队列中,从而允许其他数据包发往 第一个输出端口继续传输。 以这种方式,解决了HOL阻塞问题,而不需要显着增加输出队列数量。

    LOW COST IMPLEMENTATION FOR A DEVICE UTILIZING LOOK AHEAD CONGESTION MANAGEMENT
    2.
    发明申请
    LOW COST IMPLEMENTATION FOR A DEVICE UTILIZING LOOK AHEAD CONGESTION MANAGEMENT 有权
    使用前瞻性约束管理的设备的低成本实施

    公开(公告)号:US20110044175A1

    公开(公告)日:2011-02-24

    申请号:US12872795

    申请日:2010-08-31

    IPC分类号: H04L12/26

    CPC分类号: H04L47/6205

    摘要: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

    摘要翻译: 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外,它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息,它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时,输出队列中的数据包将发往拥塞路径,它将违规数据包置于拥塞流队列中,从而允许其他数据包发往 第一个输出端口继续传输。 以这种方式,解决了HOL阻塞问题,而不需要显着增加输出队列数量。

    Low cost implementation for a device utilizing look ahead congestion management
    3.
    发明授权
    Low cost implementation for a device utilizing look ahead congestion management 有权
    低成本实施的设备利用前瞻性拥塞管理

    公开(公告)号:US08531968B2

    公开(公告)日:2013-09-10

    申请号:US12872795

    申请日:2010-08-31

    IPC分类号: G01R31/08 H04L12/28

    CPC分类号: H04L47/6205

    摘要: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

    摘要翻译: 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外,它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息,它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时,输出队列中的数据包将发往拥塞路径,它将违规数据包置于拥塞流队列中,从而允许其他数据包发往 第一个输出端口继续传输。 以这种方式,解决了HOL阻塞问题,而不需要显着增加输出队列数量。

    Low cost implementation for a device utilizing look ahead congestion management
    4.
    发明申请
    Low cost implementation for a device utilizing look ahead congestion management 有权
    低成本实施的设备利用前瞻性拥塞管理

    公开(公告)号:US20050195845A1

    公开(公告)日:2005-09-08

    申请号:US10794067

    申请日:2004-03-05

    IPC分类号: H04L12/28

    CPC分类号: H04L47/6205

    摘要: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

    摘要翻译: 本发明利用在现有技术的传统简单排队方案中实现的每个输出端口的单独队列。 此外,它还使用分组报头中找到的信息来确定输出端口和下一个输出端口。 基于此信息,它利用专用于拥塞流或“拥塞流”队列的队列。 当交换机确定基于第一输出端口和第二后续输出端口时,输出队列中的分组将发往拥塞路径,则将违规数据包置于拥塞流队列中,从而允许其他分组发往 第一个输出端口继续传输。 以这种方式,解决了HOL阻塞问题,而不需要显着增加输出队列数量。

    System and method for storing a sequential data stream
    5.
    再颁专利
    System and method for storing a sequential data stream 有权
    用于存储顺序数据流的系统和方法

    公开(公告)号:USRE44402E1

    公开(公告)日:2013-07-30

    申请号:US12943839

    申请日:2010-11-10

    IPC分类号: G06F12/00

    CPC分类号: G11C7/1006

    摘要: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

    摘要翻译: 本发明提供了一种用于接收高速顺序数据流的改进的装置和方法。 它利用存储存储器的概念来减少用于接收数据流的输入缓冲器所需的速度和大小。 这允许设备使用大的相对较慢的存储器元件,从而允许接收设备存储大量的顺序数据。 使用作为数据写入的控制信息被存储在存储体中,重排序元件随后能够以与接收流不同的顺序从多个存储体中检索数据元素, 并将数据流重组为原始序列。

    System and method for storing a sequential data stream
    6.
    发明授权
    System and method for storing a sequential data stream 有权
    用于存储顺序数据流的系统和方法

    公开(公告)号:US07451282B2

    公开(公告)日:2008-11-11

    申请号:US11076464

    申请日:2005-03-09

    IPC分类号: G06F12/00

    CPC分类号: G11C7/1006

    摘要: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

    摘要翻译: 本发明提供了一种用于接收高速顺序数据流的改进的装置和方法。 它利用存储存储器的概念来减少用于接收数据流的输入缓冲器所需的速度和大小。 这允许设备使用大的相对较慢的存储器元件,从而允许接收设备存储大量的顺序数据。 使用作为数据写入的控制信息被存储在存储体中,重排序元件随后能够以与接收流不同的顺序从多个存储体中检索数据元素, 并将数据流重组为原始序列。

    System and method for storing a sequential data stream

    公开(公告)号:US20060203570A1

    公开(公告)日:2006-09-14

    申请号:US11076464

    申请日:2005-03-09

    IPC分类号: G11C7/10

    CPC分类号: G11C7/1006

    摘要: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

    Cache coherency mechanism
    8.
    发明申请
    Cache coherency mechanism 审中-公开
    缓存一致机制

    公开(公告)号:US20050228952A1

    公开(公告)日:2005-10-13

    申请号:US10823300

    申请日:2004-04-13

    IPC分类号: G06F12/00 G06F12/08

    CPC分类号: G06F12/0817

    摘要: The present invention minimizes the amount of traffic that traverses the fabric in support of the cache coherency protocol. It also allows rapid transmission of all traffic associated with the cache coherency protocol, so as to minimize latency and maximize performance. A fabric is used to interconnect a number of processing units together. The switches are able to recognize incoming traffic related to the cache coherency protocol and then move these messages to the head of that switch's output queue to insure fast transmission. Also, the traffic related to the cache coherency protocol can interrupt an outgoing message, further reducing latency. The switch incorporates a memory element, dedicated to the cache coherency protocol, which tracks the contents of all of the caches of all of the processors connected to the fabric. In this way, the fabric can selectively transmit traffic only to the processors where it is relevant.

    摘要翻译: 本发明最大限度地减少了支持高速缓存一致性协议的通过结构的业务量。 它还允许与高速缓存一致性协议相关联的所有业务的快速传输,以便最小化等待时间并最大化性能。 织物用于将多个处理单元互连在一起。 交换机能够识别与缓存一致性协议相关的传入流量,然后将这些消息移动到该交换机的输出队列的头部以确保快速传输。 此外,与缓存一致性协议相关的流量可以中断外发消息,进一步减少延迟。 该交换机包含专用于高速缓存一致性协议的存储器元件,其跟踪连接到该结构的所有处理器的所有高速缓存的内容。 以这种方式,结构可以选择性地将流量传输到与其相关的处理器。