公开(公告)号：US20120049834A1

公开(公告)日：2012-03-01

申请号：US13318580

申请日：2010-05-07

申请人： David Pommerenke ,  Keong Kam ,  Ankit Bhargava ,  Peng Shao ,  Xin Chang ,  Hongyu Li

发明人： David Pommerenke ,  Keong Kam ,  Ankit Bhargava ,  Peng Shao ,  Xin Chang ,  Hongyu Li

IPC分类号： G05F3/08 ,  H01F41/02

CPC分类号： H02M1/34 ,  H02M2001/348 ,  Y10T29/4902

摘要： A snubber circuit for use with a DC/DC converter broadly comprises a snubber resistor connected in parallel with a snubber inductor. The DC/DC converter may include a voltage source, a first switching element, a second switching element, an output inductor, and an output capacitor. The voltage source may include a positive terminal and a negative terminal connected to a ground node. The first switching element may include a first terminal connected to the positive terminal of the voltage source The second switching element may be connected to a second terminal of the first switching element. The series combination of the output inductor and the output capacitor may be connected between the second terminal of the first switching element and the ground node. The snubber circuit may be connected between the second switching element and the ground node.

摘要翻译： 用于DC / DC转换器的缓冲电路广泛地包括与缓冲电感器并联连接的缓冲电阻器。 DC / DC转换器可以包括电压源，第一开关元件，第二开关元件，输出电感器和输出电容器。 电压源可以包括连接到接地节点的正极端子和负极端子。 第一开关元件可以包括连接到电压源的正极端子的第一端子。第二开关元件可以连接到第一开关元件的第二端子。 输出电感器和输出电容器的串联组合可以连接在第一开关元件的第二端子和接地节点之间。 缓冲电路可以连接在第二开关元件和接地节点之间。

公开(公告)号：US08645779B2

公开(公告)日：2014-02-04

申请号：US13530081

申请日：2012-06-21

申请人： Rajan Aggarwal ,  Ashutosh Anand ,  Ankit Bhargava ,  Mishika Singla ,  Prashant K. Sonone

发明人： Rajan Aggarwal ,  Ashutosh Anand ,  Ankit Bhargava ,  Mishika Singla ,  Prashant K. Sonone

IPC分类号： G01R31/28

CPC分类号： G01R31/318544

摘要： A method for scan testing an integrated circuit that includes a plurality of on-chip logic modules includes configuring the integrated circuit for module level scan testing and chip level scan testing by way of an external automatic test pattern generator (ATPG) tool. The ATPG tool generates first and second sets of test patterns for module level and chip level scan testing of the integrated circuit. The ATPG tool generates the second set of test patterns by excluding the design faults which have already been targeted during the module level scan testing, from the first set of test patterns and reduces the overall time required for scan testing the integrated circuit.

摘要翻译： 一种用于扫描测试包括多个片上逻辑模块的集成电路的方法包括通过外部自动测试模式发生器（ATPG）工具来配置用于模块级扫描测试的集成电路和芯片级扫描测试。 ATPG工具生成集成电路的模块级和芯片级扫描测试的第一组和第二组测试模式。 ATPG工具通过从第一组测试模式中排除已经在模块级扫描测试期间已经定向的设计故障，生成第二组测试模式，并减少了对集成电路进行扫描测试所需的总体时间。

公开(公告)号：US20130346819A1

公开(公告)日：2013-12-26

申请号：US13530081

申请日：2012-06-21

申请人： Rajan Aggarwal ,  Ashutosh Anand ,  Ankit Bhargava ,  Mishika Singla ,  Prashant K. Sonone

发明人： Rajan Aggarwal ,  Ashutosh Anand ,  Ankit Bhargava ,  Mishika Singla ,  Prashant K. Sonone

IPC分类号： G01R31/3177

CPC分类号： G01R31/318544

摘要： A method for scan testing an integrated circuit that includes a plurality of on-chip logic modules includes configuring the integrated circuit for module level scan testing and chip level scan testing by way of an external automatic test pattern generator (ATPG) tool. The ATPG tool generates first and second sets of test patterns for module level and chip level scan testing of the integrated circuit. The ATPG tool generates the second set of test patterns by excluding the design faults which have already been targeted during the module level scan testing, from the first set of test patterns and reduces the overall time required for scan testing the integrated circuit.

摘要翻译： 一种用于扫描测试包括多个片上逻辑模块的集成电路的方法包括通过外部自动测试模式发生器（ATPG）工具来配置用于模块级扫描测试的集成电路和芯片级扫描测试。 ATPG工具生成集成电路的模块级和芯片级扫描测试的第一组和第二组测试模式。 ATPG工具通过从第一组测试模式中排除已经在模块级扫描测试期间已经定向的设计故障，生成第二组测试模式，并减少了对集成电路进行扫描测试所需的总体时间。