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公开(公告)号：US20110148892A1
公开(公告)日：2011-06-23
申请号：US12654385
申请日：2009-12-17
IPC分类号： G09G5/36
CPC分类号： G06T11/40 , G09G5/14 , G09G5/393 , G09G2360/122
摘要： A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.
摘要翻译： 使用延迟绘制命令的窗口显示器通过处理写入帧缓冲器30的瓦片22的绘图命令来进行操作，以形成一个或多个新的像素值存储在瓦片存储器40中。表示瓦片内的哪些像素的脏像素数据 存储器是存储新像素值的脏像素，并且还形成了瓦片存储器内的哪些像素不存储新像素值的清洁像素。 根据脏像素数据，存储在瓦片存储器中的新像素值被写入帧缓冲存储器。 对应于瓷砖内存中清洁像素的帧缓冲存储器中存储的像素在未写入时保持不变。
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公开(公告)号：US08803898B2
公开(公告)日：2014-08-12
申请号：US12654385
申请日：2009-12-17
申请人： David Robert Shreiner , Ian Victor Devereux , Edvard Sørg{dot over (a)}rd , Thomas Jeremy Olson
发明人： David Robert Shreiner , Ian Victor Devereux , Edvard Sørg{dot over (a)}rd , Thomas Jeremy Olson
CPC分类号： G06T11/40 , G09G5/14 , G09G5/393 , G09G2360/122
摘要： A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.
摘要翻译： 使用延迟绘制命令的窗口显示器通过处理写入帧缓冲器30的瓦片22的绘图命令来进行操作，以形成一个或多个新的像素值存储在瓦片存储器40中。表示瓦片内的哪些像素的脏像素数据 存储器是存储新像素值的脏像素，并且还形成了瓦片存储器内的哪些像素不存储新像素值的清洁像素。 根据脏像素数据，存储在瓦片存储器中的新像素值被写入帧缓冲存储器。 对应于瓷砖内存中清洁像素的帧缓冲存储器中存储的像素在未写入时保持不变。
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公开(公告)号：US20120206455A1
公开(公告)日：2012-08-16
申请号：US12929807
申请日：2011-02-16
IPC分类号： G06T17/00
CPC分类号： G06T15/005
摘要： A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list. This enables the same graphics processing unit to be used for both binning and rasterization operations, significantly reducing the size of the graphics system, whilst also allowing improvements in performance and energy consumption.
摘要翻译： 提供了一种基于瓦片的图形系统和这种系统的操作方法，用于为包括多个瓦片的帧生成图形数据。 提供图形处理电路，其被布置为在第一操作模式和第二操作模式之间切换。 在第一操作模式中，图形处理电路接收用于该帧的多个图形基元，并且执行合并操作，以便为多个瓦片中的每一个确定标识与该瓦片相交的图形基元的瓦片列表。 在第二操作模式中，图形处理电路接收分配的瓦片的瓦片列表，并执行光栅化操作以根据瓦片列表生成所分配的瓦片的图形数据。 这使得能够将相同的图形处理单元用于分档和光栅化操作，显着减小图形系统的尺寸，同时还允许改进性能和能量消耗。
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公开(公告)号：US08339409B2
公开(公告)日：2012-12-25
申请号：US12929807
申请日：2011-02-16
CPC分类号： G06T15/005
摘要： A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list. This enables the same graphics processing unit to be used for both binning and rasterization operations, significantly reducing the size of the graphics system, while also allowing improvements in performance and energy consumption.
摘要翻译： 提供了一种基于瓦片的图形系统以及这种系统的操作方法，用于为包括多个瓦片的帧生成图形数据。 提供图形处理电路，其被布置为在第一操作模式和第二操作模式之间切换。 在第一操作模式中，图形处理电路接收用于该帧的多个图形基元，并且执行合并操作，以便为多个瓦片中的每一个确定标识与该瓦片相交的图形基元的瓦片列表。 在第二操作模式中，图形处理电路接收分配的瓦片的瓦片列表，并执行光栅化操作以根据瓦片列表生成所分配的瓦片的图形数据。 这使得能够将相同的图形处理单元用于分档和光栅化操作，显着减小图形系统的尺寸，同时还允许改进性能和能量消耗。
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公开(公告)号：US09922442B2
公开(公告)日：2018-03-20
申请号：US13552090
申请日：2012-07-18
CPC分类号： G06T15/005 , G06T17/20
摘要： A graphics processing unit having a shader execution unit for executing a plurality of shader routines in order to perform a predetermined sequence of shader operations. The shader operations include a tessellation operation which receives as inputs tessellation control data and an input list of input data for M input vertices, and generates at least output data for P output vertices. For each output vertex, the controller allocates a tessellation shader routine from the set of shader routines, and the shader execution unit is configured, each time the tessellation shader routine is executed for an associated output vertex: (i) to compute, in dependence on the tessellation control data and the associated output vertex, tessellation coordinate data; and (ii) to compute from the input data for the M input vertices, and the tessellation coordinate data generated in step (i), the output data for the associated output vertex.
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