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1.发明授权Apparatus and method for dynamic frequency adjustment in a frequency synthesizer 有权频率合成器中动态频率调整的装置和方法公开(公告)号：US06522207B1
公开(公告)日：2003-02-18
申请号：US09631720
申请日：2000-08-03
IPC分类号： H03L700
摘要： An apparatus and a method for making small frequency adjustments in a frequency synthesizer. The frequency synthesizer consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and the output of the forward portion of the phase locked loop connected to a dynamically variable frequency divider. By changing the constant of division in the variable frequency divider, the output of the frequency divider can be rapidly changed in small increments. The dynamically variable frequency divider is key to this design. This digital circuit stores the current divisor value and has an input for a new divisor value. When a signal is sent to switch to the new divisor value, the circuit uses an incrementer and associated logic to rapidly change to the new constant of division.
摘要翻译： 一种用于在频率合成器中进行小频率调整的装置和方法。 频率合成器包括通过固定分频器的反馈的锁相环的前向部分和连接到动态可变分频器的锁相环的前部的输出。 通过改变可变分频器中的分频常数，分频器的输出可以以小的增量快速变化。 动态可变分频器是本设计的关键。 该数字电路存储当前除数值，并具有新的除数值的输入。 当发送信号以切换到新的除数值时，电路使用增量器和相关联的逻辑来快速变化到新的除法常数。
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2.发明授权Apparatus and method for high resolution frequency adjustment in a multistage frequency synthesizer 失效用于多级频率合成器中高分辨率频率调整的装置和方法公开(公告)号：US06566921B1
公开(公告)日：2003-05-20
申请号：US09631718
申请日：2000-08-03
IPC分类号： H03L706
CPC分类号： H03L7/23
摘要： An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.
摘要翻译： 一种用于在多级频率合成器中进行高分辨率频率调整的装置和方法。 频率合成器的初始阶段是连接到动态可变分频器的常规锁相环。 存在一个或多个中间级，其包括通过固定分频器反馈并连接到动态可变分频器的锁相环的前部。 最后一个阶段包括通过固定分频器反馈并连接到另一个固定分频器的锁相环的前向部分。 通过改变电路中可变分频器的分频常数，可以非常快速地进行微调频率调整。 调整精度取决于分频器的相对值和系统中的中间级数。
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3.发明授权System for synchronizing nodes in a heterogeneous computer system by using multistage frequency synthesizer to dynamically adjust clock frequency of the nodes 失效通过使用多级频率合成器来动态调整节点的时钟频率来同步异构计算机系统中的节点的系统公开(公告)号：US06763474B1
公开(公告)日：2004-07-13
申请号：US09631712
申请日：2000-08-03
IPC分类号： G06P112
CPC分类号： H03L7/23
摘要： An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.
摘要翻译： 用于节点同步的装置和方法，其可以用于系统中的节点不共享公共系统时钟的异构计算机系统中。 重要的时间戳附加在交易请求上。 时间戳基于“时间”值，其可以简单地是由系统时钟增加的寄存器。 由于每个节点都有自己的系统时钟，这些时钟的频率可能会偏移，这会导致时间戳值的变化。 如果值漂移太远，数据更新可能会丢失。 能够将高分辨率和快速频率调节的频率合成器连接到系统时钟。 当检测到主从时间之间的相位偏移时，可以将频率合成器输出改变少量以使两个信号回到相位。
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