Method for manufacturing display substrate
    1.
    发明授权
    Method for manufacturing display substrate 失效
    显示基板的制造方法

    公开(公告)号:US07544581B2

    公开(公告)日:2009-06-09

    申请号:US12073091

    申请日:2008-02-29

    IPC分类号: H01L21/76

    摘要: A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a material having low transmittance ratio into the marking pattern. The present invention further discloses a method for making a display substrate, including the steps: providing a substrate; forming a shadow layer on a non-active area of the substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on the shadow layer of the non-active area on the substrate; and removing a part of the shadow layer not covered by the marking pattern.

    摘要翻译: 公开了一种制造显示基板的方法,其包括以下步骤:提供基板; 在所述基板的有效区域上形成多个凸起,以及在所述基板的非有源区域上形成至少一个标记图案; 并将标记图案染色或将具有低透光率的材料填充到标记图案中。 本发明还公开了一种制造显示基板的方法,包括以下步骤:提供基板; 在所述基板的非有源区域上形成阴影层; 在所述基板的有效区域上形成多个凸起,以及在所述基板上的所述非有源区域的所述阴影层上的至少一个标记图案; 并且去除未被标记图案覆盖的阴影层的一部分。

    Method for reducing reactive ion etching (RIE) lag in semiconductor fabrication processes
    3.
    发明授权
    Method for reducing reactive ion etching (RIE) lag in semiconductor fabrication processes 有权
    在半导体制造工艺中减少反应离子蚀刻(RIE)滞后的方法

    公开(公告)号:US06900136B2

    公开(公告)日:2005-05-31

    申请号:US10094288

    申请日:2002-03-08

    CPC分类号: H01L21/30655

    摘要: A method for reducing RIE lag (reaction ion etching lag) in a deep silicon etching process forming trench openings is described. The method can be carried out by either a photolithographic means wherein trench openings of the same planar area are patterned on the silicon substrate, or by a pressure means in which the chamber pressure during the reactive ion etching process is increased to reduce or eliminate the RIE lag effect. By increasing the chamber pressure at least 50% from that normally incurred in a reactive ion etching process, and preferably at least 100%, the RIE lag effect can be completely eliminated resulting in an inversed RIE lag in which a larger etch depth is achieved for the trench openings that have the smallest width.

    摘要翻译: 描述了在形成沟槽开口的深硅蚀刻工艺中减少RIE滞后(反应离子蚀刻滞后)的方法。 该方法可以通过光刻装置进行,其中相同平面区域的沟槽开口在硅衬底上图案化,或通过压力装置进行,其中反应离子蚀刻工艺期间室压力增加以减少或消除RIE 滞后效应。 通过将腔室压力从反应离子蚀刻工艺中通常产生的压力提高至少50%,并且优选至少100%,可以完全消除RIE滞后效应,导致反转的RIE滞后,其中获得较大的蚀刻深度用于 具有最小宽度的沟槽开口。

    Canted-fiber duplex optical assembly
    4.
    发明申请
    Canted-fiber duplex optical assembly 审中-公开
    光纤双面光学组件

    公开(公告)号:US20070133928A1

    公开(公告)日:2007-06-14

    申请号:US11373186

    申请日:2006-03-13

    IPC分类号: G02B6/36

    摘要: A canted-fiber duplex optical subassembly is disclosed herein. The optical subassembly transmits and receives optical signals by way of a single optical fiber, which has a canted surface on one end. A light source sends transmission optical signals, which are refracted through the canted surface and then enter the optical fiber. Reception optical signals in the optical fiber are reflected by the canted surface and are then received by an optical detector.

    摘要翻译: 本文公开了一种倾斜光纤双工光学子组件。 光学组件通过单端光纤发射和接收光信号,该光纤在一端具有倾斜表面。 光源发送传输光信号,其通过倾斜表面折射,然后进入光纤。 光纤中的接收光信号被倾斜表面反射,然后由光学检测器接收。