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公开(公告)号:US20110320695A1
公开(公告)日:2011-12-29
申请号:US12821736
申请日:2010-06-23
申请人: Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diana L. Orf , Robert J. Sonnelitter, III
发明人: Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diana L. Orf , Robert J. Sonnelitter, III
CPC分类号: G06F12/0857 , G06F12/084 , G06F12/0846 , G06F12/0855 , G06F2212/1024 , G06F2212/281
摘要: Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.
摘要翻译: 本发明的各种实施例减轻了分级存储器存储器高速缓存结构中的繁忙时间。 在一个实施例中,与存储器高速缓存相关联的高速缓存目录被分成多个部分,每个部分与部分存储器高速缓存相关联。 支持高速缓存目录的多个部分之间的同时高速缓存查找操作和缓存写入操作。 在通信地耦合到高速缓存目录的多个部分的共享高速缓存管道中同时处理两个或更多个存储命令。
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公开(公告)号:US20110314211A1
公开(公告)日:2011-12-22
申请号:US12820511
申请日:2010-06-22
申请人: Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
发明人: Deanna P. BERGER , Michael F. Fee , Christine C. Jones , Diana L. Orf , Robert J. Sonnelitter, III
CPC分类号: G06F11/1064 , G06F12/0802
摘要: Various embodiments of the present invention merge data in a cache memory. In one embodiment a set of store data is received from a processing core. A store merge command and a merge mask from are also received from the processing core. A portion of the store data to perform a merging operation thereon is identified based on the store merge command. A sub-portion of the portion of the store data to be merged with a corresponding set of data from a cache memory is identified based on the merge mask. The sub-portion is merged with the corresponding set of data from the cache memory.
摘要翻译: 本发明的各种实施例将数据合并在高速缓冲存储器中。 在一个实施例中,从处理核心接收一组存储数据。 还从处理核心接收存储合并命令和合并掩码。 基于存储合并命令来识别用于执行其上的合并操作的存储数据的一部分。 基于合并掩码来识别与高速缓冲存储器的相应的数据集合合并的存储数据的一部分的子部分。 子部分与来自高速缓冲存储器的相应的数据集合合并。
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