公开(公告)号：US09041119B2

公开(公告)日：2015-05-26

申请号：US13465159

申请日：2012-05-07

申请人： Desmond J. Donegan, Jr. ,  Abhishek Dube ,  Steven Jones ,  Jophy S. Koshy ,  Viorel Ontalus

发明人： Desmond J. Donegan, Jr. ,  Abhishek Dube ,  Steven Jones ,  Jophy S. Koshy ,  Viorel Ontalus

IPC分类号： H01L29/02 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.

摘要翻译： 提供了一种形成具有接近应力的晶体管到晶体管的沟道区域的方法。 该方法包括在衬底的第一区域中形成第一晶体管，在衬底的第一区域的顶部上具有栅极叠层，以及邻近栅堆叠的侧壁的一组间隔物，第一区域包括源极和漏极 第一晶体管的区域; 在所述衬底的第二区域中形成第二晶体管，在所述衬底的所述第二区域的顶部上具有栅极叠层，以及邻近所述栅极叠层的侧壁的一组间隔区，所述第二区域包括所述栅极叠层的源极和漏极区域 第二晶体管; 用光致抗蚀剂掩模覆盖第一晶体管而不覆盖第二晶体管; 在所述第二晶体管的源极和漏极区域中产生凹陷; 并在凹槽中形成应力源。

公开(公告)号：US07989298B1

公开(公告)日：2011-08-02

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20110183486A1

公开(公告)日：2011-07-28

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。