公开(公告)号：US06472900B1

公开(公告)日：2002-10-29

申请号：US09874188

申请日：2001-06-04

申请人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

发明人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

IPC分类号： G01R3126

CPC分类号： G01R1/0408 ,  H01L2224/73204 ,  H01L2924/15311

摘要： A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

摘要翻译： 一种提供具有至少两个信号处理层的集成半导体衬底的电测试的方法和系统。 衬底可以设置有塑料，硅，氧化硅，氮化硅等的保护层。 待电测试的一个衬底层的选定区域通过蚀刻或以其他方式形成可控制的小孔而暴露出任何覆盖的衬底层，以暴露所选区域中的至少一个所选择的电路迹线，并将所选择的电信号施加到 跟踪。 可选地，可以形成与第一孔间隔开的第二孔，以暴露第二选择的电路迹线，从而可以测试一个或多个衬底电路中的信号传播。 孔径横截面形状可以是线性或曲线多边形或其它合适的形状。

公开(公告)号：US06246252B1

公开(公告)日：2001-06-12

申请号：US09364563

申请日：1999-07-30

申请人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

发明人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

IPC分类号： G01R3126

CPC分类号： G01R1/0408 ,  H01L2224/73204 ,  H01L2924/15311

摘要： A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

摘要翻译： 一种用于提供具有至少两个信号处理层的集成半导体衬底的电测试的方法。 衬底可以设置有塑料，硅，氧化硅，氮化硅等的保护层。 待电测试的一个衬底层的选定区域通过蚀刻或以其它方式形成任何覆盖的衬底层的可控制的小孔而露出，以暴露所选区域中的至少一个选择的电路迹线，并将选择的电信号施加到 跟踪。 可选地，可以形成与第一孔间隔开的第二孔，以暴露第二选择的电路迹线，从而可以测试一个或多个衬底电路中的信号传播。 孔径横截面形状可以是线性或曲线多边形或其它合适的形状。