公开(公告)号：US06472900B1

公开(公告)日：2002-10-29

申请号：US09874188

申请日：2001-06-04

申请人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

发明人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

IPC分类号： G01R3126

CPC分类号： G01R1/0408 ,  H01L2224/73204 ,  H01L2924/15311

摘要： A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

摘要翻译： 一种提供具有至少两个信号处理层的集成半导体衬底的电测试的方法和系统。 衬底可以设置有塑料，硅，氧化硅，氮化硅等的保护层。 待电测试的一个衬底层的选定区域通过蚀刻或以其他方式形成可控制的小孔而暴露出任何覆盖的衬底层，以暴露所选区域中的至少一个所选择的电路迹线，并将所选择的电信号施加到 跟踪。 可选地，可以形成与第一孔间隔开的第二孔，以暴露第二选择的电路迹线，从而可以测试一个或多个衬底电路中的信号传播。 孔径横截面形状可以是线性或曲线多边形或其它合适的形状。

公开(公告)号：US06246252B1

公开(公告)日：2001-06-12

申请号：US09364563

申请日：1999-07-30

申请人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

发明人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

IPC分类号： G01R3126

CPC分类号： G01R1/0408 ,  H01L2224/73204 ,  H01L2924/15311

摘要： A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

摘要翻译： 一种用于提供具有至少两个信号处理层的集成半导体衬底的电测试的方法。 衬底可以设置有塑料，硅，氧化硅，氮化硅等的保护层。 待电测试的一个衬底层的选定区域通过蚀刻或以其它方式形成任何覆盖的衬底层的可控制的小孔而露出，以暴露所选区域中的至少一个选择的电路迹线，并将选择的电信号施加到 跟踪。 可选地，可以形成与第一孔间隔开的第二孔，以暴露第二选择的电路迹线，从而可以测试一个或多个衬底电路中的信号传播。 孔径横截面形状可以是线性或曲线多边形或其它合适的形状。

公开(公告)号：US07928744B2

公开(公告)日：2011-04-19

申请号：US12326552

申请日：2008-12-02

申请人： Colin Price ,  Steven Boyle ,  Asif Ahmad

发明人： Colin Price ,  Steven Boyle ,  Asif Ahmad

IPC分类号： G05F1/00

CPC分类号： G01R19/1659 ,  G01R31/31932 ,  G01R31/362 ,  G01R31/3658 ,  G01R35/00

摘要： A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating the capacitor from the signal injector and voltage reference, and connecting the capacitor between the first and second input nodes such that the voltage stored on the capacitor is overwritten by the voltage difference between the first and second nodes, and iii) and reconnecting the capacitor to the comparator and monitoring the comparator's output.

摘要翻译： 一种包括自检功能的测量装置，所述电路包括电容器; 第一至第四开关; 测试信号注射器; 具有信号输入和参考输入的至少一个比较器，所述第一开关插入所述电容器的第一板和第一输入节点之间，所述第二开关插入在所述电容器的第二板和第二输入节点之间，所述第三开关 开关插入在电容器的第一板和比较器的信号输入端之间，第四开关插在电容器的第二板和电压基准之间，其中自检功能包括以下步骤：i）操作信号注入器 以产生表示第一和第二输入节点之间的期望电压差超出范围电压的第一信号，并且使用该信号使至少一个比较器将其输出置于误差状态，并为电容器充电 超出范围电压，ii）将电容器与信号注入器和参考电压隔离，并将电容器连接在第一和第二电容器之间 输入节点，使得存储在电容器上的电压被第一和第二节点之间的电压差覆盖，以及iii）并且将电容器重新连接到比较器并监视比较器的输出。

公开(公告)号：US06573590B1

公开(公告)日：2003-06-03

申请号：US10074721

申请日：2002-02-11

申请人： Sergiu Radu ,  John E. Will ,  Steven Boyle ,  David Hockanson

发明人： Sergiu Radu ,  John E. Will ,  Steven Boyle ,  David Hockanson

IPC分类号： H01L23552

CPC分类号： H01L23/49838 ,  H01L23/10 ,  H01L23/49827 ,  H01L23/552 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/3011

摘要： An integrated circuit package comprising EMI containment features. The EMI containment features include a first EMI containment configuration and a second EMI containment configuration. The second EMI containment configuration is disposed around the first EMI containment configuration. The first and second EMI containment configurations include vias coupled to at least one ground plane of the integrated circuit package.

摘要翻译： 一种集成电路封装，包括EMI抑制特征。 EMI抑制特征包括第一EMI容纳配置和第二EMI容纳配置。 第二EMI容纳构造设置在第一EMI容纳构造周围。 第一和第二EMI容纳配置包括耦合到集成电路封装的至少一个接地平面的通孔。

公开(公告)号：US20050235349A1

公开(公告)日：2005-10-20

申请号：US11159505

申请日：2005-06-22

申请人： Steven Boyle ,  Debra Kirchhoff

发明人： Steven Boyle ,  Debra Kirchhoff

IPC分类号： H04L29/06 ,  H04L9/00

CPC分类号： H04L63/029

摘要： A high-bandwidth direct communication path between two clients is used for voice or video calls over the Internet. An opening or a window in a firewall is made for the direct path by sending a null packet out from inside the firewall. The null packet can be a UDP packet directed to a UDP port of the other client. Initially, each client makes a TCP connection to port 80 of an external manager. Each client registers its UDP port number with the external manager. A call request from one client to the external manager results in a message from the external manager to the other client. The other client then creates the window in its firewall by transmitting the null UDP packet. Then the external manager is notified and tells the calling client to begin sending UDP packets directly to the other client through the firewall window.

摘要翻译： 两个客户端之间的高带宽直接通信路径用于通过因特网进行语音或视频通话。 通过从防火墙内部发送一个空数据包，在防火墙中打开一个窗口或直接路径。 空分组可以是指向另一个客户端的UDP端口的UDP分组。 最初，每个客户端与外部管理器的端口80进行TCP连接。 每个客户端将其UDP端口号注册到外部管理器。 从一个客户端到外部管理员的呼叫请求会导致从外部管理器向另一个客户端发送的消息。 然后，另一个客户端通过发送空UDP数据包在其防火墙中创建窗口。 然后通知外部管理员，并通过呼叫客户端通过防火墙窗口直接发送UDP数据包到其他客户端。