公开(公告)号：US08582338B1

公开(公告)日：2013-11-12

申请号：US13149878

申请日：2011-05-31

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: Ternary CAM cells are disclosed that include a compare circuit that includes a discharge path having a single pull-down transistor coupled between the match line and ground potential.

Abstract translation: 公开了三元CAM单元，其包括比较电路，该比较电路包括具有耦合在匹配线和地电位之间的单个下拉晶体管的放电路径。

公开(公告)号：US20120327696A1

公开(公告)日：2012-12-27

申请号：US13167646

申请日：2011-06-23

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced.

Abstract translation: 通过减少匹配线在失配条件下放电的电荷量，在搜索关键字和存储在器件阵列中的数据之间的比较操作期间减少CAM器件的功耗。 更具体地，对于一些实施例，CAM阵列的每一行包括在匹配条件期间将匹配线放电到虚拟接地节点而不是接地电位的电路。 由于虚拟接地节点上的电位大于地电位，所以与下一次比较操作期间将匹配线充电到逻辑高状态相关联的功耗降低。

公开(公告)号：US08773880B2

公开(公告)日：2014-07-08

申请号：US13167646

申请日：2011-06-23

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced.

Abstract translation: 通过减少匹配线在失配条件下放电的电荷量，在搜索关键字和存储在器件阵列中的数据之间的比较操作期间减少CAM器件的功耗。 更具体地，对于一些实施例，CAM阵列的每一行包括在匹配条件期间将匹配线放电到虚拟接地节点而不是接地电位的电路。 由于虚拟接地节点上的电位大于地电位，所以与下一次比较操作期间将匹配线充电到逻辑高状态相关联的功耗降低。

公开(公告)号：US08675798B1

公开(公告)日：2014-03-18

申请号：US12978045

申请日：2010-12-23

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: H04L7/02

CPC classification number: H03K5/135

Abstract: Systems, methods, and circuits provide phase inversion of a clock signal. A first clock signal is received. A phase inversion signal indicates the existence of a 180 degree phase difference between the first clock signal and a second clock signal. As a result of the phase inversion signal indicating the 180 degree phase difference, the system, methods and circuits adapt the first clock signal by extending the first clock signal by a phase such that the first clock signal's rising edges and falling edges align with the second clock signal's rising edges and falling edges. As a result, the 180 degree phase difference between the clock signals is eliminated.

Abstract translation: 系统，方法和电路提供时钟信号的相位反转。 接收第一时钟信号。 相位反转信号表示在第一时钟信号和第二时钟信号之间存在180度相位差。 作为指示180度相位差的相位反转信号的结果，系统，方法和电路通过将第一时钟信号延伸一个相位使第一时钟信号适应第一时钟信号，使得第一时钟信号的上升沿和下降沿与第二时钟信号对准 时钟信号的上升沿和下降沿。 结果，消除了时钟信号之间的180度相位差。

公开(公告)号：US08493763B1

公开(公告)日：2013-07-23

申请号：US13283422

申请日：2011-10-27

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A CAM array includes a plurality of regular rows and a reference row. Each regular row is partitioned into a plurality of row segments, with each row segment including a number of CAM cells coupled to a corresponding match line segment. The reference row generates self-timed control signals for corresponding segments of the regular rows. Control circuits selectively enable a respective row segment in response to a logical combination of match results in a previous row segment and an associated one of the self-timed control signals.

Abstract translation: CAM阵列包括多个常规行和参考行。 每个常规行被划分成多个行段，其中每个行段包括耦合到对应的匹配线段的多个CAM单元。 参考行为常规行的相应段生成自定时控制信号。 控制电路响应于先前行段中的匹配结果和相关联的一个自定时控制信号的逻辑组合，选择性地启用相应的行段。

公开(公告)号：US08625320B1

公开(公告)日：2014-01-07

申请号：US13216104

申请日：2011-08-23

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: Quaternary CAM cells are provided that include a compare circuit having a discharge path between a match line and ground potential, the single discharge path consisting essentially of a single transistor. In an embodiment, the single transistor has a gate coupled to a pull-down node and the compare circuit includes first and second gating transistors connected in series between the pull-down node and a ground potential, the first gating transistor having a gate to receive a comparand bit, and the second gating transistor having a gate to receive a complemented comparand bit.

Abstract translation: 提供了第四纪CAM单元，其包括具有在匹配线和接地电位之间的放电路径的比较电路，单个放电路径基本上由单个晶体管组成。 在一个实施例中，单晶体管具有耦合到下拉节点的栅极，并且比较电路包括串联连接在下拉节点和地电位之间的第一和第二门控晶体管，第一选通晶体管具有门以接收 比较位，并且第二门控晶体管具有用于接收补码比较位的栅极。

公开(公告)号：US08462532B1

公开(公告)日：2013-06-11

申请号：US13015543

申请日：2011-01-27

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, with each parallel path consisting of a single pull-down transistor having a gate selectively coupled to the stored data value in response to a comparand value.

Abstract translation: 提供了第四纪CAM单元，其包括一个或多个比较电路，每个比较电路具有耦合在匹配线和地电位之间的最小数量的下拉晶体管。 对于一些实施例，比较电路包括匹配线和地电位之间的两条并行路径，每条并行路径由单个下拉晶体组成，其具有响应于比较值有选择地耦合到所存储的数据值的栅极。

公开(公告)号：US07589362B1

公开(公告)日：2009-09-15

申请号：US11764157

申请日：2007-06-15

Applicant: Dimitri Argyres ,  Bindiganavale S. Nataraj

Inventor： Dimitri Argyres ,  Bindiganavale S. Nataraj

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L23/585 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.

Abstract translation: 包括衬底，形成在衬底上的多个器件层的集成电路（IC）器件以及产生指示器件修订版本的修订代码的多个多级修正（MLR）结构。 每个MLR组结构包括多个MLR单元，并且包括具有耦合到MLR单元的输出的多个输入的奇偶校验电路，并且具有用于生成修订代码的对应位的输出。 每个MLR组结构中的MLR单元被分配给不同的设备层，并且每个设备层被分配给每个MLR组结构中的一个MLR单元。 每个修订代码位可由相应MLR组结构中的任何MLR单元控制。

公开(公告)号：US06964028B2

公开(公告)日：2005-11-08

申请号：US10431383

申请日：2003-05-08

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5031

Abstract: A method, and a corresponding data structure, are used for designing a circuit by displaying signal information on a schematic diagram of the circuit to aid in resolving design problems. A circuit design is stored as data in a computer memory. An E-CAD tool software application is performed on the design to create an archive file containing x-y display coordinates for displaying the signals as part of a schematic. The archive file contains names and locations of all signals. The design is analyzed to extract signal information. Timing information may be extracted using a timing analyzer. The information is stored in a data file, such as a timing data file in the computer memory. Timing information and signal display coordinate information may be combined into a new archive file that is used to create a schematic diagram of the circuit, or a portion of the circuit, in which the timing information is displayed near the signals and signal names. Based on the displayed timing information, the designer can identify and attempt to resolve problem signals in the design.

Abstract translation: 通过在电路的示意图上显示信号信息来帮助解决设计问题，通过一种方法和相应的数据结构来设计电路。 电路设计作为数据存储在计算机存储器中。 在设计上执行E-CAD工具软件应用程序，以创建一个包含x-y显示坐标的存档文件，用于显示信号作为原理图的一部分。 归档文件包含所有信号的名称和位置。 分析设计以提取信号信息。 可以使用定时分析器提取定时信息。 信息存储在数据文件中，例如计算机存储器中的定时数据文件。 定时信息和信号显示坐标信息可以被组合成新的档案文件，其用于创建电路的示意图或电路的一部分，其中在信号和信号名称附近显示定时信息。 基于显示的定时信息，设计人员可以识别并尝试解决设计中的问题信号。

公开(公告)号：US08837188B1

公开(公告)日：2014-09-16

申请号：US13167552

申请日：2011-06-23

Applicant: Ganesh Krishnamurthy ,  Dimitri Argyres

Inventor： Ganesh Krishnamurthy ,  Dimitri Argyres

IPC: G11C15/00 ,  G11C15/04 ,  G11C11/56

CPC classification number: G11C15/04 ,  G11C11/56 ,  G11C15/00 ,  G11C15/046

Abstract: A content addressable memory (CAM) row is disclosed. The CAM row includes one or more compare circuits coupled between a match line and a virtual-ground line. The compare circuits are configured to compare a search key with CAM cell data words. The CAM row also includes a pre-charge circuit controlled by a pre-charge signal, and includes a tank capacitor. The pre-charge circuit is configured to pre-charge the match line to a supply voltage in response to assertion of the pre-charge signal. A pull-down transistor dynamically discharges the virtual-ground line to ground potential.

Abstract translation: 公开了内容可寻址存储器（CAM）行。 CAM行包括耦合在匹配线和虚拟地线之间的一个或多个比较电路。 比较电路被配置为将搜索关键字与CAM单元数据字进行比较。 CAM行还包括由预充电信号控制的预充电电路，并且包括储能电容器。 预充电电路被配置为响应于预充电信号的断言将匹配线预充电到电源电压。 下拉晶体管将虚拟地线动态放电到地电位。