公开(公告)号：US20100011136A1

公开(公告)日：2010-01-14

申请号：US12564610

申请日：2009-09-22

申请人： Dominic Go ,  Mark D. HAYTER ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. HAYTER ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US08028103B2

公开(公告)日：2011-09-27

申请号：US12564610

申请日：2009-09-22

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US07548997B2

公开(公告)日：2009-06-16

申请号：US11620875

申请日：2007-01-08

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

公开(公告)号：US20110307759A1

公开(公告)日：2011-12-15

申请号：US13216411

申请日：2011-08-24

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F11/08 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US07620746B2

公开(公告)日：2009-11-17

申请号：US11238850

申请日：2005-09-29

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US20070073915A1

公开(公告)日：2007-03-29

申请号：US11238850

申请日：2005-09-29

申请人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F3/00

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

公开(公告)号：US20070130384A1

公开(公告)日：2007-06-07

申请号：US11620875

申请日：2007-01-08

申请人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US20130322753A1

公开(公告)日：2013-12-05

申请号：US13485421

申请日：2012-05-31

申请人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

发明人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

IPC分类号： G06T5/00

CPC分类号： G06T5/001 ,  G06K9/38 ,  G06T1/20 ,  G06T5/002 ,  G06T5/003 ,  G06T5/008 ,  G06T5/50 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20028 ,  G06T2207/20208

摘要： Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.

公开(公告)号：US09105078B2

公开(公告)日：2015-08-11

申请号：US13485421

申请日：2012-05-31

申请人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

发明人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

IPC分类号： G06K9/00 ,  G06T5/00

CPC分类号： G06T5/001 ,  G06K9/38 ,  G06T1/20 ,  G06T5/002 ,  G06T5/003 ,  G06T5/008 ,  G06T5/50 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20028 ,  G06T2207/20208

摘要： Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.

摘要翻译： 提供了本地色调映射的系统和方法。 在一个示例中，电子设备包括电子显示器，成像设备和图像信号处理器。 电子显示器可以显示第一位深度的图像，并且成像装置可以包括获得比第一位深度更高的位深度的图像数据的图像传感器。 图像信号处理器可以处理图像数据，并且可以包括本地色调映射逻辑，其可以将空间上变化的本地色调曲线应用于图像数据的像素，以便在显示器上显示时保持局部对比度。 本地色调映射逻辑可以平滑应用于像素和另一附近像素之间的强度差超过阈值的局部色调曲线。

公开(公告)号：US09077943B2

公开(公告)日：2015-07-07

申请号：US13484741

申请日：2012-05-31

申请人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

发明人： Suk Hwan Lim ,  D. Amnon Silverstein ,  Guy Cote ,  Steven David Hordley ,  Graham Finlayson ,  Weichun Ku ,  Joseph P. Bratt

IPC分类号： G06K9/00 ,  H04N9/73 ,  H04N5/14 ,  H04N9/04

CPC分类号： H04N9/73 ,  H04N5/142 ,  H04N9/045 ,  H04N9/735 ,  H04N2209/046

摘要： Systems and methods for generating local image statistics are provided. In one example, an image signal processing system may include a statistics pipeline with image processing logic and local image statistics collection logic. The image processing logic may receive and process pixels of raw image data. The local image statistics collection logic may generate a local histogram associated with a luminance of the pixels of a first block of pixels of the raw image data or a thumbnail in which a pixel of the thumbnail represents a downscaled version of the luminance of the pixels of the first block of the pixel. The raw image data may include many other blocks of pixels of the same size as the first block of pixels.

摘要翻译： 提供了生成本地图像统计信息的系统和方法。 在一个示例中，图像信号处理系统可以包括具有图像处理逻辑和本地图像统计信息收集逻辑的统计流水线。 图像处理逻辑可以接收和处理原始图像数据的像素。 本地图像统计收集逻辑可以生成与原始图像数据的第一像素块的像素的亮度相关联的局部直方图或缩略图，其中缩略图的像素表示缩略图的像素的亮度 像素的第一个块。 原始图像数据可以包括与第一像素块相同尺寸的许多其他像素块。