公开(公告)号：US5530706A

公开(公告)日：1996-06-25

申请号：US539382

申请日：1995-10-05

Applicant: Don D. Josephson ,  Barry J. Arnold

Inventor： Don D. Josephson ,  Barry J. Arnold

IPC: G01R31/3185 ,  G06F15/20 ,  H04B17/00

CPC classification number: G01R31/318577 ,  G01R31/318541

Abstract: A test system for a digital integrated circuit in which internal states of the integrated circuit are captured non-destructively while the digital circuit is operating at normal clock speed. Cells for capturing states are sequentially connected into shift registers. Once internal states are latched within cells, the captured states are serially shifted out a test port while the integrated circuit continues to operate. State sampling is triggered internally via a software command or externally via an external signal synchronized to an internal clock.

Abstract translation: 一种用于数字集成电路的测试系统，其中在数字电路以正常时钟速度操作时非集成电路的内部状态被非破坏性地捕获。 用于捕获状态的单元被顺序地连接到移位寄存器中。 一旦内部状态被锁存在单元内，则捕获的状态在集成电路继续工作时，串行地移出测试端口。 状态采样通过软件命令内部触发，或通过与内部时钟同步的外部信号从外部触发。

公开(公告)号：US07250800B2

公开(公告)日：2007-07-31

申请号：US11179400

申请日：2005-07-12

Applicant: Quanhong Zhu ,  Don D. Josephson

Inventor： Quanhong Zhu ,  Don D. Josephson

IPC: H03K3/017

CPC classification number: H03K5/156 ,  H03K5/05 ,  H03K2005/00156

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

公开(公告)号：US20070013422A1

公开(公告)日：2007-01-18

申请号：US11179400

申请日：2005-07-12

Applicant: Quanhong Zhu ,  Don D. Josephson

Inventor： Quanhong Zhu ,  Don D. Josephson

IPC: H03K3/017

CPC classification number: H03K5/156 ,  H03K5/05 ,  H03K2005/00156

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract translation: 在一个实施例中，时钟脉冲宽度控制电路包括多个定时器电路，以从输入时钟信号，对应的多个与门产生相应的多个延迟脉冲信号，每个与门从延迟脉冲产生输出信号 信号和输入时钟信号，以及选择电路以选择输出信号之一。

公开(公告)号：US06683483B1

公开(公告)日：2004-01-27

申请号：US10280472

申请日：2002-10-25

Applicant: Jeffrey Paul Witte ,  Quanhong Zhu ,  Don D. Josephson

Inventor： Jeffrey Paul Witte ,  Quanhong Zhu ,  Don D. Josephson

IPC: H03K3017

CPC classification number: H03K5/1565 ,  H03K5/135

Abstract: Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.

Abstract translation: 两个同步触发器将慢时钟的转换同步到快速时钟。 同步慢时钟版本的状态由时钟在快速时钟边缘的最后一个状态触发器存储。 最后状态触发器通过逻辑与同步慢时钟的版本进行比较，以产生宽度由快速时钟的相位或快速时钟周期确定的宽度的脉冲。