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    ADAPTIVE SLEW RATE CONTROL FOR SWITCHING POWER DEVICES
    3.
    发明申请
    ADAPTIVE SLEW RATE CONTROL FOR SWITCHING POWER DEVICES 有权
    用于切换电源设备的自适应频率控制

    公开(公告)号：US20170012618A1

    公开(公告)日：2017-01-12

    申请号：US14796749

    申请日：2015-07-10

    Applicant: Texas Instruments Incorporated

    Inventor： KANNAN KRISHNA

    IPC: H03K17/16 ,  H03K7/08 ,  H03K5/156

    CPC classification number: H03K17/165 ,  H03K5/156 ,  H03K7/08 ,  H03K17/166

    Abstract: An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range.

    Abstract translation: 自适应驱动器包括具有至少一个用于驱动开关晶体管的控制节点的至少一个驱动晶体管的栅极驱动器，该驱动晶体管包括提供Vout的输出节点（OUT）。 可调电流源与驱动晶体管串联，在OUT和地之间的高通滤波器（HPF）用于检测开关晶体管的转换速率，并输出具有至少单调的峰值电压振幅的电压脉冲（Vslp） 在切换期间反映Vout的斜率。 检测信号处理电路耦合到HPF的输出以用于处理Vslp，并且压摆率控制电路具有耦合到检测信号处理电路的输出的输入。 转换速率控制电路的输出耦合到电流源，用于控制其电流电平以改变开关晶体管的转换速率，以提供期望的转换速率范围。

    Transforming a phase-locked-loop generated chip clock signal to a local clock signal
    4.
    发明授权
    Transforming a phase-locked-loop generated chip clock signal to a local clock signal 有权
    将锁相环生成的芯片时钟信号转换为本地时钟信号

    公开(公告)号：US09401698B1

    公开(公告)日：2016-07-26

    申请号：US14716992

    申请日：2015-05-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Yuen Hung Chan ,  Juergen Pille ,  Rolf Sautter ,  Tobias Werner

    IPC: G11C8/00 ,  H03K3/017 ,  H03K5/156 ,  G11C11/419 ,  G11C7/22

    CPC classification number: H03K5/13 ,  G11C7/222 ,  G11C11/417 ,  H03K3/017 ,  H03K5/156 ,  H03K5/1565 ,  H03K2005/00019

    Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.

    Abstract translation: 提供了电子电路和存储器电路，用于实现用于将芯片时钟信号转换为本地时钟信号的方法。 该方法包括：响应于芯片时钟信号产生第一时钟信号，第一控制信号和第二控制信号; 通过以第二时钟延迟延迟所述第一时钟信号来产生第二时钟信号; 通过以第二控制信号从高到低的方式延迟具有脉冲宽度延迟的第二时钟信号来产生第一控制信号和第二控制信号，其中第一控制信号在控制信号延迟之后从高到低变化， 低，反之亦然; 以及基于所述第二时钟信号产生所述本地时钟信号。

    Dual-complementary integrating duty cycle detector with dead band noise rejection
    5.
    发明授权
    Dual-complementary integrating duty cycle detector with dead band noise rejection 有权
    具有死区噪声抑制的双互补集成占空比检测器

    公开(公告)号：US09246475B2

    公开(公告)日：2016-01-26

    申请号：US14249088

    申请日：2014-04-09

    Applicant: United Memories, Inc.

    Inventor： Oscar Frederick Jones, Jr. ,  Jon Allan Faue

    IPC: H03K5/156 ,  H03K3/017

    CPC classification number: H03K3/017 ,  H03K5/156

    Abstract: A method for correcting the duty cycle of a clock signal uses two-dual-slope integrators with two comparators; each comparator is connected to both integrators and configured to include a “dead band” when the input pulse duty cycle is at or near 50%. One comparator detects when duty cycle is high and the other comparator detects when the duty cycle is low. When the duty cycle is within the “dead band” range, neither comparator goes valid. This provides an analog filter where the output comparators will not instantaneously switch between opposite duty cycle correction states. When the duty cycle is greater or less than 50%, the integrated voltages on the two integrators move in opposite directions producing twice the signal magnitude on differential inputs of the comparators, as compared with using a single integrator architecture.

    Abstract translation: 用于校正时钟信号的占空比的方法使用具有两个比较器的双斜率积分器; 每个比较器连接到两个积分器，并且当输入脉冲占空比为或接近50％时被配置为包括“死区”。 一个比较器检测占空比为高电平，另一个比较器检测占空比为低时。 当占空比在“死区”范围内时，两个比较器都无效。 这提供了模拟滤波器，其中输出比较器不会在相反的占空比校正状态之间瞬间切换。 当占空比大于或小于50％时，与使用单个积分器架构相比，两个积分器上的积分电压在相反方向上移动，产生两倍于比较器差分输入的信号幅度。

    METHOD FOR PROCESSING A SIGNAL SUPPLIED BY A BI-DIRECTIONAL SENSOR AND CORRESPONDING DEVICE
    6.
    发明申请
    METHOD FOR PROCESSING A SIGNAL SUPPLIED BY A BI-DIRECTIONAL SENSOR AND CORRESPONDING DEVICE 有权
    用于处理由双向传感器和相应装置提供的信号的方法

    公开(公告)号：US20150315988A1

    公开(公告)日：2015-11-05

    申请号：US14647249

    申请日：2013-11-26

    Applicant: CONTINENTAL AUTOMOTIVE FRANCE ,  CONITINENTAL AUTOMOTIVE GMBH

    Inventor： Jerome HOU

    IPC: F02D28/00

    CPC classification number: F02D28/00 ,  F02D41/009 ,  F02D41/0097 ,  H03K5/156 ,  H03K5/26

    Abstract: A method and device for processing a signal (CRK) provided by a bidirectional sensor, the method includes the following steps: generation of a first signal (CRK_CNT) utilizing all the slots of the signal provided by the sensor, generation of a second signal (CRK_FW) utilizing the slots corresponding to a first direction of transit, generation of a third signal (CRK_BW) utilizing the slots corresponding to a second direction of transit, connection of the first signal to the input of the first electronic component, connection of the second and third signals to a second component, detection by the second component of edges of the signals received, change of the value of the predefined threshold (THMI) in the first component upon each detection of an edge.

    Abstract translation: 一种用于处理由双向传感器提供的信号（CRK）的方法和装置，该方法包括以下步骤：利用由传感器提供的信号的所有时隙产生第一信号（CRK_CNT），产生第二信号 CRK_FW），利用对应于第一传输方向的时隙，利用与第二传输方向相对应的时隙产生第三信号（CRK_BW），将第一信号连接到第一电子部件的输入端，连接第二信号 以及第三信号到第二分量，由所述第二分量检测所接收的信号的边缘，在每次检测到边缘时，改变所述第一分量中的所述预定义阈值（THMI）。

    Method and system for removing a pulse having a different pulse width relative to that of other pulses in a clock signal of an analog to digital converter
    7.
    发明授权
    Method and system for removing a pulse having a different pulse width relative to that of other pulses in a clock signal of an analog to digital converter 有权
    用于去除具有与模数转换器的时钟信号中的其它脉冲不同的脉冲宽度的脉冲的方法和系统

    公开(公告)号：US08994407B1

    公开(公告)日：2015-03-31

    申请号：US14051614

    申请日：2013-10-11

    Applicant: Marvell International Ltd.

    Inventor： Chi Fung Cheng ,  Pantas Sutardja

    IPC: G01R29/02 ,  H03K9/08 ,  H03K5/156

    CPC classification number: H03K5/156 ,  G11B5/09 ,  G11B20/10222 ,  G11B2220/2516 ,  H03K5/1252

    Abstract: A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.

    Abstract translation: 系统包括基于第一时钟信号将模拟信号转换为数字信号的ADC。 第一电路基于数字信号产生第二时钟信号。 内插器产生第二时钟信号的相位延迟版本和第三时钟信号。 基于第二时钟信号和相位延迟版本产生第三时钟信号，并且包括从第二时钟信号转换到相位延迟版本。 第三时钟信号包括具有第一脉冲宽度的脉冲和具有第二脉冲宽度的脉冲。 由于从第二时钟信号向第三时钟信号的转变，第二脉冲宽度与第一脉冲宽度不同。 第二电路从第三时钟信号中去除具有第二脉冲宽度的脉冲以产生第一时钟信号。

    Duty cycle based phase interpolators and methods for use
    9.
    发明授权
    Duty cycle based phase interpolators and methods for use 有权
    基于占空比的相位插值器和使用方法

    公开(公告)号：US08278987B2

    公开(公告)日：2012-10-02

    申请号：US12854771

    申请日：2010-08-11

    Applicant: Gideon Yong

    Inventor： Gideon Yong

    IPC: H03K3/017

    CPC classification number: H03K5/156 ,  H03K5/1565 ,  H03K7/08 ,  H03K2005/00052

    Abstract: Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.

    Abstract translation: 公开了基于占空比的相位内插器，以及用于实现基于占空比的相位内插器的方法。 一个这样的相位插值器包括被配置为产生第一占空比信号的第一脉冲宽度调制器和被配置为产生第二占空比信号的第二脉冲宽度调制器。 相位插值器还包括逻辑单元，其被配置为合并第一占空比信号和第二占空比信号，以根据第一和第二占空比信号产生具有可控相位的周期性数字信号。

    FRACTIONAL FREQUENCY DIVIDER
    10.
    发明申请
    FRACTIONAL FREQUENCY DIVIDER 有权
    分数分频器

    公开(公告)号：US20120001665A1

    公开(公告)日：2012-01-05

    申请号：US13172491

    申请日：2011-06-29

    Applicant: Nicolas Regimbal ,  Franck Badets ,  Yann Deval ,  Jean-Baptiste Begueret

    Inventor： Nicolas Regimbal ,  Franck Badets ,  Yann Deval ,  Jean-Baptiste Begueret

    IPC: H03K21/00

    CPC classification number: H03K5/156 ,  H03K21/10 ,  H03K23/662 ,  H03K23/68

    Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

    Abstract translation: 一种分数分频器，包括用于产生具有针对原始定时信号的每k个脉冲具有j个脉冲的降频定时信号的分频单元，其中j和k各自是整数; 以及相位校正电路，其适于选择性地将所述降频定时信号的第j个脉冲移位第一固定时间段。

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