公开(公告)号：US06812761B2

公开(公告)日：2004-11-02

申请号：US10670697

申请日：2003-09-24

申请人： Thomas D. Simon ,  Rajeevan Amirtharajah

发明人： Thomas D. Simon ,  Rajeevan Amirtharajah

IPC分类号： H03K3017

CPC分类号： H03K5/1534 ,  H03K5/06 ,  H03K5/13

摘要： The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

公开(公告)号：US06788120B1

公开(公告)日：2004-09-07

申请号：US10460031

申请日：2003-06-11

申请人： Andy T. Nguyen

发明人： Andy T. Nguyen

IPC分类号： H03K3017

CPC分类号： H03K5/1565

摘要： Counter-based duty cycle correction (DCC) circuits and methods. A first counter is periodically enabled to count for one input clock period. After completion of the count, the result is divided by two and stored in a register. Thus, the value stored in the register represents a point halfway through the input clock period. Each time the input clock signal changes from a first state to a second state, an output clock generator also changes the output clock signal from the first state to the second state, and the second counter is enabled. A comparator compares the value in the second counter to the value stored in the register. When the second counter has reached the value stored in the register, the half-way point of the input clock cycle has been reached, and the output clock generator changes the output clock signal from the second state back to the first state.

摘要翻译： 基于计数器的占空比校正（DCC）电路和方法。 周期性地使第一个计数器对一个输入时钟周期进行计数。 计数完成后，将结果除以2并存储在寄存器中。 因此，存储在寄存器中的值表示输入时钟周期中途的点。 每当输入时钟信号从第一状态变为第二状态时，输出时钟发生器也将输出时钟信号从第一状态改变到第二状态，并且第二计数器被使能。 比较器将第二个计数器中的值与存储在寄存器中的值进行比较。 当第二个计数器达到存储在寄存器中的值时，输入时钟周期的中间点已经到达，输出时钟发生器将输出时钟信号从第二个状态改变到第一个状态。

公开(公告)号：US06784709B2

公开(公告)日：2004-08-31

申请号：US10198954

申请日：2002-07-22

申请人： Je-Hun Ryu

发明人： Je-Hun Ryu

IPC分类号： H03K3017

CPC分类号： G06F1/04 ,  H03K5/1565

摘要： A clock generator to produce internal clock signals with a controlled pulse width in a synchronous semiconductor memory device. The clock generator includes a clock input circuit receiving an external clock signal, a reference voltage signal and an option signal, and outputting first and second clock signals; a clock driver receiving the first clock signal and outputting an internal clock signal in response to the option signal; and a detector receiving the second clock signal and outputting the option signal in response to a control signal.

摘要翻译： 时钟发生器，用于在同步半导体存储器件中产生具有受控脉冲宽度的内部时钟信号。 时钟发生器包括接收外部时钟信号的时钟输入电路，参考电压信号和选项信号，并输出第一和第二时钟信号; 接收所述第一时钟信号并响应于所述选项信号输出内部时钟信号的时钟驱动器; 以及检测器，其接收第二时钟信号并响应于控制信号输出选项信号。

公开(公告)号：US06774692B2

公开(公告)日：2004-08-10

申请号：US10124023

申请日：2002-04-17

申请人： Young-hwan Kim ,  Chung Choo Chung ,  Haiwon Lee

发明人： Young-hwan Kim ,  Chung Choo Chung ,  Haiwon Lee

IPC分类号： H03K3017

CPC分类号： G01Q60/34 ,  H03K5/02 ,  H03K5/05 ,  Y10S977/85

摘要： An apparatus and method for providing an input signal having a desired pulse width and amplitude to atomic force miscoscopes (AFMs) for use in nano-lithography are provided. An input signal providing apparatus for a contact type AFM includes: a pulse width adjusting unit which adjusts the width of a positive pulse of an input square wave to a predetermined pulse width; and an amplitude adjusting unit which adjusts the amplitude of the positive pulse of the square wave to a predetermined voltage. An input signal providing method for the contact type AFM uses the apparatus having this structure. An input signal providing apparatus for a non-contact type AFM further includes a square pulse generating unit which generates a square pulse having a predetermined phase in synchronization with an input resonance signal, and an input signal providing method for the non-contact type AFM further involves generating the square pulse having a predetermined phase in synchronization with the input resonance signal. As a result, more precise nano-lithography can be achieved using an AFM to which the apparatus and method described above are applied.

摘要翻译： 提供了一种用于提供具有期望的脉冲宽度和幅度的输入信号的装置和方法，用于在纳米光刻中使用的原子力测量仪（AFM）。 用于接触型AFM的输入信号提供装置包括：脉冲宽度调整单元，其将输入方波的正脉冲的宽度调整到预定的脉冲宽度; 以及幅度调整单元，其将所述方波的正脉冲的幅度调整到预定电压。 用于接触型AFM的输入信号提供方法使用具有这种结构的装置。 用于非接触型AFM的输入信号提供装置还包括平方脉冲产生单元，其产生与输入谐振信号同步的具有预定相位的方波脉冲，以及用于非接触型AFM的输入信号提供方法 包括与输入的谐振信号同步地产生具有预定相位的平方脉冲。 因此，可以使用应用上述装置和方法的AFM来实现更精确的纳米光刻。

公开(公告)号：US06670838B1

公开(公告)日：2003-12-30

申请号：US10288786

申请日：2002-11-05

申请人： Wangpeng Cao

发明人： Wangpeng Cao

IPC分类号： H03K3017

CPC分类号： H03K5/1565

摘要： A nominal 50% duty cycle input CLKIN clock signal is processed by an adaptive circuit that outputs complementary CLK and CLKB clock signals whose duty cycle is continuously and automatically maintained at substantially 50%. The circuit includes a duty cycle adjustor circuit comprising inverter stages whose VTH is adjusted by a control voltage VC to vary duty cycle of the CLKIN signal passing through the stages. The inverter output signal is converted to the differential CLK, CLKB signals, which are low pass filtered to obtain DC voltages that are input to a differential operational amplifier whose output is control signal VC. Using the ensured substantially 50% duty cycle for CLK (or CLKB) enables data to be clocked or latch-transferred between IC stages substantially error free even if IC stage setup time varies, and clock frequency is increased. CLK duty cycle can be held to 50%±0.1% even if CLKIN duty cycle varies from 33% to 67%.

摘要翻译： 额定50％的占空比输入CLKIN时钟信号由自适应电路处理，自适应电路输出互补的CLK和CLKB时钟信号，其占空比连续自动保持在50％左右。 该电路包括占空比调节器电路，该电路包括通过控制电压VC调节其VTH以改变通过级的CLKIN信号的占空比的反相器级。 逆变器输出信号被转换为低通滤波的差分CLK，CLKB信号，以获得输入到输出为控制信号VC的差分运算放大器的直流电压。 使用确保CLK（或CLKB）的基本上50％的占空比使得即使IC级建立时间变化并且时钟频率增加，数据也可在IC级之间进行时钟或锁存传输，基本上无误。 即使CLKIN占空比从33％变化到67％，CLK占空比可以保持在50％±0.1％。

公开(公告)号：US06542015B2

公开(公告)日：2003-04-01

申请号：US09820193

申请日：2001-03-28

申请人： Jian Zhou ,  Robert Payne ,  Huanzhang Huang ,  Douglas Wente

发明人： Jian Zhou ,  Robert Payne ,  Huanzhang Huang ,  Douglas Wente

IPC分类号： H03K3017

CPC分类号： H03K5/1565 ,  H03K5/007

摘要： A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage. The correction differential current is provided to the pair of summing nodes to produce a corrected differential current as the sum of the uncorrected differential current and the correction differential current so as to control the timing of the crossover of the corrected differential current at the pair of summing nodes to provide duty cycle correction. Finally, the corrected differential square wave clock signal is provided by generating a differential square wave voltage corresponding to the corrected differential current.

摘要翻译： 一种用于校正具有正弦特性的未校正差分时钟信号的占空比的方法和装置，并输出校正的差分方波时钟信号。 在该方法中，未校正的差分时钟信号作为未校正的差分电流被提供给一对求和节点。 产生校正差分电压作为对应于校正的差分时钟信号的反相的信号，并且具有相对于校正差分电压的另一个的共模电压的一个校正差分信号的共模电压，该校正差分电压取决于 未校正的差分时钟信号的占空比。 产生对应于校正差分电压的校正差分电流。 校正差分电流被提供给一对求和节点，以产生校正的差分电流作为未校正的差分电流和校正差分电流的和，以便控制在一对求和中的校正的差分电流的交叉的定时 节点提供占空比校正。 最后，通过产生对应于校正的差分电流的差分方波电压来提供校正的差分方波时钟信号。

公开(公告)号：US06538484B1

公开(公告)日：2003-03-25

申请号：US10100273

申请日：2002-03-18

申请人： Elchanan Rappaport ,  Bernard Harris

发明人： Elchanan Rappaport ,  Bernard Harris

IPC分类号： H03K3017

CPC分类号： H03K7/08 ,  H02M3/157 ,  H03K7/06 ,  H03M1/822

摘要： In a control system, with a defined clock rate C—a method and apparatus for generating a train of pulses whose mean level is proportional to a given number V, having N equispaced possible values, the pulses to be applied to a given low-pass process, the method comprising generating a train of constant-amplitude pulses at a rate that is considerably greater than C/N, when the width of each pulse is an integer multiple of a clock period, 1/C, and the widths of all pulses are not necessarily equal.

摘要翻译： 在控制系统中，具有定义的时钟速率Ca方法和装置，用于产生其平均电平与给定数量V成比例的脉冲序列，具有N个等间隔的可能值，要施加到给定低通处理的脉冲， 该方法包括：当每个脉冲的宽度是时钟周期的整数倍时，1 / C，并且所有脉冲的宽度不是，以相当大于C / N的速率产生恒定幅度脉冲串 必然相等

公开(公告)号：US06535040B2

公开(公告)日：2003-03-18

申请号：US09929522

申请日：2001-08-14

申请人： Yeon-jae Jung ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

发明人： Yeon-jae Jung ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

IPC分类号： H03K3017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

摘要翻译： 占空比校正电路包括占空比校正器和检测电路。 占空比校正器响应于第一检测信号和具有第一占空比的第一控制信号产生具有比第一占空比更高的等效程度的第二占空比的第一输入信号。 检测电路响应于第一输入信号产生第一检测信号。 检测电路包括具有第一和第二电流源的电流源和电耦合到第一和第二电流源的偏置电路，并响应于第一输入信号控制第一和第二电流源的偏置。

公开(公告)号：US06525580B2

公开(公告)日：2003-02-25

申请号：US10173015

申请日：2002-06-18

申请人： Frank W. Singor

发明人： Frank W. Singor

IPC分类号： H03K3017

CPC分类号： H03K5/15 ,  G06F1/08 ,  G11C27/024

摘要： A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.

公开(公告)号：US06518809B1

公开(公告)日：2003-02-11

申请号：US09920029

申请日：2001-08-01

申请人： Prasad Rao Kotra

发明人： Prasad Rao Kotra

IPC分类号： H03K3017

CPC分类号： H03K5/1565 ,  H03K3/017 ,  H03K5/08

摘要： An apparatus including a driver and an adjustment circuit. The driver circuit may be configured to generate an output signal in response to a clock input signal and an adjustment signal. The adjustment circuit may be configured to generate the adjustment signal in response to the output signal. The adjustment signal may be configured to correct a duty cycle of the output signal.

摘要翻译： 一种包括驱动器和调整电路的装置。 驱动器电路可以被配置为响应于时钟输入信号和调整信号而产生输出信号。 调整电路可以被配置为响应于输出信号而产生调整信号。 调整信号可以被配置为校正输出信号的占空比。