-
公开(公告)号：US06857049B1
公开(公告)日：2005-02-15
申请号：US09651488
申请日：2000-08-30
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from managing the process of flushing old data from the second level cache memory. In the present invention, the second level cache memory is a store-in memory. Therefore, when data is to be deleted from the second level cache memory, a determination is made whether the data has been modified by the processor. If the data has been modified, the data must be rewritten to lower level memory. To free the second level cache memory for storage of the newly requested data, the data to be flush is loaded into a flush buffer for storage during the rewriting process.
摘要翻译： 一种用于提高采用多级高速缓冲存储器系统的数据处理系统的效率的方法和装置。 通过管理从第二级高速缓冲存储器刷新旧数据的过程导致效率。 在本发明中，第二级高速缓冲存储器是存储存储器。 因此，当要从第二级高速缓冲存储器中删除数据时，确定数据是否已被处理器修改。 如果数据被修改，则数据必须重新写入较低级别的内存。 要释放用于存储新请求的数据的第二级高速缓冲存储器，要刷新的数据将在重写过程中加载到刷新缓冲区中以进行存储。
-
公开(公告)号：US06697925B1
公开(公告)日：2004-02-24
申请号：US09748535
申请日：2000-12-22
IPC分类号： G06F1200
CPC分类号： G06F12/0815 , G06F1/14
摘要： A method of and apparatus for improving the efficiency of a data processing system employing multiple dayclocks using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from dedicating a separate individual dayclock to each of the multiple instruction processors within the data processing system thereby decreasing access time and user queuing. These individual dayclocks are each incremented at one microsecond intervals. However, these individual dayclocks require periodic synchronization to avoid system level time-tagging problems. This synchronization occurs at 20 microsecond intervals using the cache coherency maintenance hardware of the system.
摘要翻译： 一种使用保持系统级高速缓冲存储器的一致性的设施来提高使用多个时钟的数据处理系统的效率的方法和装置。 这些效率是由专用于数据处理系统中的多个指令处理器的每一个单独的时钟而导致的，从而减少访问时间和用户排队。 这些单独的日钟分别以1微秒的间隔递增。 然而，这些单独的时钟需要定期同步以避免系统级时间标记问题。 该同步使用系统的高速缓存一致性维护硬件以20微秒的间隔进行。
-
公开(公告)号：US5875201A
公开(公告)日：1999-02-23
申请号：US777037
申请日：1996-12-30
CPC分类号： G06F11/1008 , G06F11/1064
摘要： Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.
摘要翻译： 用于检测和校正使用奇偶校验错误检测的系统中的存储器存储数据错误的方法和装置。 在存储器存储装置中检测到的错误导致正在报告奇偶校验错误，从而导致对应的地址位置被去激活。 一旦停用，在该地址位置不进行进一步的读取或写入达预定的时间段。 奇偶校验错误报告和地址禁用在没有访问时间损失的情况下完成，并且需要减少I / O引脚数。
-
公开(公告)号：US5617375A
公开(公告)日：1997-04-01
申请号：US577908
申请日：1995-12-04
CPC分类号： G04G99/006 , G06F1/14
摘要： An apparatus for and method of efficiently providing a modular dayclock within a data processing system. This is accomplished by dividing the dayclock hardware into a number of dayclock modules configured to operate in a bit serial fashion. This allows the dayclock to accommodate a variety of dayclock word widths by simply varying the number of dayclock modules provided. Further, since the dayclock may operate serially, rather than in parallel fashion, the number of dayclock module I/O's and board route channels may be substantially reduced. Finally, all control logic may be provided directly in the dayclock modules, thereby eliminating the need for a central dayclock controller.
摘要翻译： 一种在数据处理系统内有效提供模块化时钟的装置和方法。 这通过将日钟硬件分成多个配置为以串行方式操作的日间钟模块来实现。 这样可以通过简单地改变所提供的日时钟模块的数量来使时钟适应各种日时钟字宽。 此外，由于日时钟可以顺序地而不是并行地进行操作，因此可以显着地减少日时钟模块I / O和板路由信道的数量。 最后，所有的控制逻辑可以直接在日时钟模块中提供，从而不需要中央的时钟控制器。
-
公开(公告)号：US6055607A
公开(公告)日：2000-04-25
申请号：US773717
申请日：1996-12-23
CPC分类号： G06F13/18
摘要： A method of interfacing multiple requests using a request hold register, a multiplexer and a snapshot register with multiple requests directed into both the request hold register and a multiplexer which prevents forwarding the requests to the snapshot register if the snapshot register is not in a receiving condition but if the snapshot register is in a receiving condition allows the request to immediately enter snapshot register without having to wait for the next clock cycle.
摘要翻译： 一种使用请求保持寄存器，多路复用器和具有多个请求的快照寄存器来连接多个请求的方法，所述多个请求被引导到请求保持寄存器和多路复用器中，如果快照寄存器不处于接收状态，则该多路复用器防止将请求转发到快照寄存器 但如果快照寄存器处于接收状态，则允许请求立即输入快照寄存器，而不必等待下一个时钟周期。
-
-
-
-
搜索结果
5 条记录 (耗时 0.019 秒)
