公开(公告)号：US20070019660A1

公开(公告)日：2007-01-25

申请号：US11512031

申请日：2006-08-28

申请人： Donald Primrose ,  I. Denton

发明人： Donald Primrose ,  I. Denton

IPC分类号： H04L12/56

CPC分类号： H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

公开(公告)号：US20070019659A1

公开(公告)日：2007-01-25

申请号：US11512028

申请日：2006-08-28

申请人： Donald Primrose ,  I. Denton

发明人： Donald Primrose ,  I. Denton

IPC分类号： H04L12/56

CPC分类号： H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

摘要翻译： 提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。 缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。 在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。 用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。 在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。

公开(公告)号：US20060291464A1

公开(公告)日：2006-12-28

申请号：US11511944

申请日：2006-08-28

申请人： Donald Primrose ,  I. Denton

发明人： Donald Primrose ,  I. Denton

IPC分类号： H04L12/56

CPC分类号： H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

摘要翻译： 提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。 缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。 在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。 用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。 在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。