公开(公告)号：US20070058985A1

公开(公告)日：2007-03-15

申请号：US11513676

申请日：2006-08-30

申请人： I. Denton ,  Bruce Murdock ,  James Gimlett ,  Edward Hershberg ,  Scott Lowrey ,  Richard Booman ,  Alfred She

发明人： I. Denton ,  Bruce Murdock ,  James Gimlett ,  Edward Hershberg ,  Scott Lowrey ,  Richard Booman ,  Alfred She

IPC分类号： H04B10/00

CPC分类号： H04J3/1617 ,  H04J2203/0085 ,  H04J2203/0089 ,  H04L69/12 ,  H04L69/18

摘要： An optical networking module is formed with an integrated module including optical, optical-electrical and protocol processing components, and complementary software. In one embodiment, the integral protocol processing component is a single ASIC and supports multiple protocols. The module is further equipped with support control electronics in support of control functions to manage the optical, optical-electrical as well as the multi-protocol processing component. The integrated module together with the complementary control software present to an optical networking equipment designer/developer a singular component that handles optical to electrical and electrical to optical conversion, as well as data link and physical sub-layer processing for a selected one of a plurality of datacom and telecom protocols, spanning local, regional as well as wide area networks. The integrated module and complementary control software further presents to the optical networking designer/developer a unified software interface for managing-the various components and functions.

摘要翻译： 光网络模块形成有包括光学，光电和协议处理组件以及补充软件的集成模块。 在一个实施例中，集成协议处理组件是单个ASIC并且支持多种协议。 该模块还配备了支持控制电子设备，以支持控制功能，以管理光学，光电以及多协议处理组件。 该集成模块与互补控制软件一起提交给光网络设备设计者/开发人员，处理光电到电和电到光转换的单一组件，以及用于多个选定的一个的数据链路和物理子层处理 数据通信和电信协议，跨越本地，区域和广域网。 集成模块和互补控制软件还向光网络设计人员/开发人员提供了一个用于管理各种组件和功能的统一软件界面。

公开(公告)号：US20070019660A1

公开(公告)日：2007-01-25

申请号：US11512031

申请日：2006-08-28

申请人： Donald Primrose ,  I. Denton

发明人： Donald Primrose ,  I. Denton

IPC分类号： H04L12/56

CPC分类号： H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

公开(公告)号：US20070133616A1

公开(公告)日：2007-06-14

申请号：US11469403

申请日：2006-08-31

申请人： Richard Keller ,  I. Denton

发明人： Richard Keller ,  I. Denton

IPC分类号： H04J3/07 ,  H04J3/00

CPC分类号： H04J3/12 ,  H04J3/1611

摘要： An insertion apparatus receives a byte value from a signaling channel, locates a particular unused byte location within an overhead portion of a synchronous optical network (SONET) frame, and inserts the byte value from the signaling channel into the particular unused byte location. An extraction apparatus receives a synchronous optical network (SONET) frame, locates a particular byte location within an overhead portion of the SONET frame that is unused for SONET purposes, and captures a byte value from the particular byte location, wherein the byte value comprises a signaling channel.

摘要翻译： 插入装置从信令信道接收字节值，将特定未使用的字节位置定位在同步光网络（SONET）帧的开销部分内，并将来自信令信道的字节值插入特定的未使用字节位置。 提取装置接收同步光网络（SONET）帧，将SONET帧的开销部分内的特定字节位置定位于SONET目的未使用，并从特定字节位置捕获字节值，其中字节值包括 信令通道。

公开(公告)号：US20060280124A1

公开(公告)日：2006-12-14

申请号：US11509948

申请日：2006-08-25

申请人： I. Denton ,  Richard Keller

发明人： I. Denton ,  Richard Keller

IPC分类号： H04J1/16

CPC分类号： H04L43/50 ,  H04L43/0811 ,  H04L43/0847 ,  H04L49/254 ,  H04L49/30 ,  H04L49/555 ,  H04L69/22 ,  H04L2012/5628

摘要： Methods and apparatus provide single or multi-port, flexible, cost-effective, built-in self-test capabilities for network communications equipment, such as for example switches, and programmably generate, and subsequently analyze, one or more sequences of test packets, wherein the test packets simulate at least two flows of traffic. Such test packets can have programmable headers, payloads, and duty cycle. A line card embodying the present invention may generate its own traffic pattern, which may be similar or identical, to traffic patterns observed on Internet backbones. These traffic patterns may contain a bimodal distribution of control packets interspersed with data packets wherein the control packets and data packets are relatively short and long respectively. A plurality of test packet generators/receivers can be deployed in a network communications device having a plurality of ports. In such a configuration, test generator/receiver is associated with each of the plurality of ports. Under software control, test packets can be sent from at least any one of the plurality of ports to at least any other one of the plurality of ports. In this way, an in-circuit testing procedure may be implemented without having to disconnect line cards from the switch and connect the switch to expensive external test equipment.

公开(公告)号：USRE43420E1

公开(公告)日：2012-05-29

申请号：US12205593

申请日：2008-09-05

申请人： Richard B. Keller ,  Claude I. Denton

发明人： Richard B. Keller ,  Claude I. Denton

IPC分类号： H04L12/56

CPC分类号： H04J3/12 ,  H04J3/1611

摘要： An insertion apparatus receives a byte value from a signaling channel, locates a particular unused byte location within an overhead portion of a synchronous optical network (SONET) frame, and inserts the byte value from the signaling channel into the particular unused byte location. An extraction apparatus receives a synchronous optical network (SONET) frame, locates a particular byte location within an overhead portion of the SONET frame that is unused for SONET purposes, and captures a byte value from the particular byte location, wherein the byte value comprises a signaling channel.

摘要翻译： 插入装置从信令信道接收字节值，将特定未使用的字节位置定位在同步光网络（SONET）帧的开销部分内，并将来自信令信道的字节值插入特定的未使用字节位置。 提取装置接收同步光网络（SONET）帧，将SONET帧的开销部分内的特定字节位置定位于SONET目的未使用，并从特定字节位置捕获字节值，其中字节值包括 信令通道。

公开(公告)号：US20070019659A1

公开(公告)日：2007-01-25

申请号：US11512028

申请日：2006-08-28

申请人： Donald Primrose ,  I. Denton

发明人： Donald Primrose ,  I. Denton

IPC分类号： H04L12/56

CPC分类号： H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

摘要翻译： 提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。 缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。 在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。 用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。 在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。

公开(公告)号：US20060291464A1

公开(公告)日：2006-12-28

申请号：US11511944

申请日：2006-08-28

申请人： Donald Primrose ,  I. Denton

发明人： Donald Primrose ,  I. Denton

IPC分类号： H04L12/56

CPC分类号： H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

摘要翻译： 提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。 缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。 在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。 用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。 在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。

公开(公告)号：US20060133411A1

公开(公告)日：2006-06-22

申请号：US11343387

申请日：2006-01-30

申请人： I. Denton ,  James Gimlett

发明人： I. Denton ,  James Gimlett

IPC分类号： H04L12/66 ,  H04J3/16

CPC分类号： H04L29/06 ,  H04L69/08 ,  H04L69/18 ,  Y10S370/907

摘要： A networking processor is formed with selected ones of one or more system interfaces, one or more network/intermediate interfaces, a plurality of data link sub-layer control/processing blocks, and a plurality of physical sub-layer coders/decoders and processing units. The elements are provisioned in a combinatorially selectable manner, enabling the single networking processor to be able to selectively facilitate data trafficking in accordance with a selected one of a plurality of protocols. The protocols include at least one each a datacom and a telecom protocol. Accordingly, the network processor supports data traffics spanning local, regional and wide area networks. In one embodiment, the traffic data may be framed or streaming data being transmitted/received in accordance with a selected one of a plurality frame based protocols and a plurality of variants of a synchronous protocol. The frame based protocols may also be frame based protocols encapsulated with the synchronous protocol.