公开(公告)号：US07646444B2

公开(公告)日：2010-01-12

申请号：US11873767

申请日：2007-10-17

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US07145620B2

公开(公告)日：2006-12-05

申请号：US10317591

申请日：2002-12-12

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/1343 ,  G02F1/136

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrode. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

公开(公告)号：US07289171B2

公开(公告)日：2007-10-30

申请号：US11551450

申请日：2006-10-20

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US20080030638A1

公开(公告)日：2008-02-07

申请号：US11873767

申请日：2007-10-17

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US20100012941A1

公开(公告)日：2010-01-21

申请号：US12570505

申请日：2009-09-30

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： H01L27/12 ,  H01L21/77

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US08355088B2

公开(公告)日：2013-01-15

申请号：US13372016

申请日：2012-02-13

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line, a storage electrode line, a gate insulating layer, a semiconductor island formed on the gate insulating layer, and a data line and a drain electrode formed thereon. The data line and drain electrode are covered with a passivation layer. A pixel electrode is formed on the passivation layer and connected to the drain electrode through a contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode overlaps the gate line and data line and has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线，存储电极线，栅极绝缘层，形成在栅极绝缘层上的半导体岛，以及形成在其上的数据线和漏电极。 数据线和漏电极被钝化层覆盖。 像素电极形成在钝化层上并通过接触孔连接到漏电极。 TFT阵列面板被覆盖有大致沿着TFT阵列板的左上角或右下角或像素电极的方向摩擦的取向层。 像素电极与栅极线和数据线重叠，并且具有位于像素电极的左上角附近的扩展，以增加像素电极与栅极线和/或数据线之间的相应重叠区域的宽度。

公开(公告)号：US20120178197A1

公开(公告)日：2012-07-12

申请号：US13372016

申请日：2012-02-13

申请人： DONG-GYU KIM ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： DONG-GYU KIM ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： H01L33/08

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line, a storage electrode line, a gate insulating layer, a semiconductor island formed on the gate insulating layer, and a data line and a drain electrode formed thereon. The data line and drain electrode are covered with a passivation layer. A pixel electrode is formed on the passivation layer and connected to the drain electrode through a contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode overlaps the gate line and data line and has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线，存储电极线，栅极绝缘层，形成在栅极绝缘层上的半导体岛，以及形成在其上的数据线和漏电极。 数据线和漏电极被钝化层覆盖。 像素电极形成在钝化层上并通过接触孔连接到漏电极。 TFT阵列面板被覆盖有大致沿着TFT阵列板的左上角或右下角或像素电极的方向摩擦的取向层。 像素电极与栅极线和数据线重叠，并且具有位于像素电极的左上角附近的扩展，以增加像素电极与栅极线和/或数据线之间的相应重叠区域的宽度。

公开(公告)号：US08130357B2

公开(公告)日：2012-03-06

申请号：US12570505

申请日：2009-09-30

申请人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu Kim ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G02F1/1339

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes a substrate, a first gate line and a second gate line disposed on the substrate, a storage electrode line disposed on the substrate, a first data line intersecting the first and second gate lines, a second data line intersecting the first and second gate lines and spaced apart from the first data line, a drain electrode facing a part of the first data line and the second data line, an organic insulating layer disposed on the first data line and the second data line, the organic insulating layer having a contact hole exposing the drain electrode, a pixel electrode disposed on the organic insulating layer, the pixel electrode electrically connected to the drain electrode, and a storage electrode making a storage conductor with the pixel electrode, wherein the pixel electrode comprises a first part overlapping the first data line, and a second part overlapping the second data line, and wherein the width of the first part is different from that of the second part.

摘要翻译： TFT阵列面板包括衬底，设置在衬底上的第一栅极线和第二栅极线，设置在衬底上的存储电极线，与第一和第二栅极线相交的第一数据线，与第一栅极线相交的第二数据线 和第二栅极线，与第一数据线间隔开，面对第一数据线和第二数据线的一部分的漏电极，设置在第一数据线和第二数据线上的有机绝缘层，有机绝缘层 具有露出漏电极的接触孔，设置在有机绝缘层上的像素电极，与漏电极电连接的像素电极，以及与像素电极形成存储导体的存储电极，其中，像素电极包括第一部分 与第一数据线重叠，第二部分与第二数据线重叠，并且其中第一部分的宽度与第二部分的宽度不同 。

公开(公告)号：US20070046569A1

公开(公告)日：2007-03-01

申请号：US11551450

申请日：2006-10-20

申请人： Dong-Gyu KIM ,  Hyang-Shik Kong ,  Jang-Soo Kim

发明人： Dong-Gyu KIM ,  Hyang-Shik Kong ,  Jang-Soo Kim

IPC分类号： G09G3/04

CPC分类号： G02F1/136213 ,  G02F1/1337 ,  G02F1/133784 ,  G02F1/134336 ,  G02F1/136227 ,  G02F2201/123

摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。 栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。 在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。 数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。 像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。 像素电极具有大致矩形形状并且与栅极线和数据线重叠。 像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

公开(公告)号：US08068077B2

公开(公告)日：2011-11-29

申请号：US12407626

申请日：2009-03-19

申请人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

发明人： Myung-Jae Park ,  Hyang-Shik Kong ,  Myung-Koo Hur ,  Jong-Woong Chang ,  Seong-Young Lee ,  Dong-Gyu Kim

IPC分类号： G09G3/36

CPC分类号： G02F1/13458 ,  G02F1/1345

摘要： A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

摘要翻译： 提供薄膜晶体管阵列面板，其包括：显示单元阵列电路，包括多个栅极线，多条数据线，多个薄膜晶体管和多个像素电极; 栅极驱动电路，向栅极线提供栅极信号; 以及连接到栅极驱动电路并且包括彼此分离的第一和第二线段的信号线以及通过至少暴露第一和第二线中的至少一个的接触孔连接到第一和第二线段的连接构件 细分。