SEMICONDUCTOR DEVICE INCLUDING RECESSED CHANNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING RECESSED CHANNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
    包括被记录的通道晶体管的半导体器件及其制造方法

    公开(公告)号:US20110278662A1

    公开(公告)日:2011-11-17

    申请号:US13096053

    申请日:2011-04-28

    IPC分类号: H01L29/78

    摘要: A semiconductor device including a recessed channel transistor, and a method of manufacturing the same, provide: a substrate in which an isolation trench is provided; an isolation layer provided in the isolation trench so as to define a pair of source/drain regions in the substrate; a gate pattern provided in the isolation trench between the pair of source/drain regions, the gate pattern having a top surface at a same level as a top surface of the isolation layer and having a bottom surface at a lower depth than the pair of source/drain regions with respect to a top surface of the substrate; and a gate insulating layer provided between the substrate and the gate pattern at a bottom surface of the isolation trench.

    摘要翻译: 包括凹陷沟道晶体管的半导体器件及其制造方法提供:其中提供隔离沟槽的衬底; 隔离层,设置在所述隔离沟槽中,以便在所述衬底中限定一对源/漏区; 栅极图案,其设置在所述一对源极/漏极区域之间的隔离沟槽中,所述栅极图案具有与所述隔离层的顶表面相同水平面的顶表面,并且具有比所述一对源极更低深度的底表面 /漏极区域相对于衬底的顶表面; 以及在隔离沟槽的底表面处设置在衬底和栅极图案之间的栅极绝缘层。

    Method of fabricating semiconductor device
    3.
    发明申请
    Method of fabricating semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号:US20080014708A1

    公开(公告)日:2008-01-17

    申请号:US11819072

    申请日:2007-06-25

    申请人: Young-mok Kim

    发明人: Young-mok Kim

    IPC分类号: H01L21/762

    摘要: Disclosed is a method of fabricating a semiconductor device having improved processing stability. A protection layer may be formed on a semiconductor substrate. A sacrificial layer having an etch selectivity with respect to the protection layer may be formed on the protection layer. A part of the sacrificial layer may be selectively etched, thereby forming an alignment key. An aligned well may be formed using the alignment key. An aligned isolation layer may be formed in the semiconductor substrate having the well formed therein, using the alignment key.

    摘要翻译: 公开了一种制造具有改善的处理稳定性的半导体器件的方法。 保护层可以形成在半导体衬底上。 可以在保护层上形成具有相对于保护层的蚀刻选择性的牺牲层。 可以选择性地蚀刻牺牲层的一部分,从而形成对准键。 可以使用对准键形成对准的井。 可以使用对准键在其中形成有阱的半导体衬底中形成对准的隔离层。