公开(公告)号：US12132116B2

公开(公告)日：2024-10-29

申请号：US17814164

申请日：2022-07-21

申请人： Micron Technology, Inc.

发明人： Akira Goda ,  Marc Aoulaiche

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/267 ,  H01L29/66 ,  H01L29/786 ,  H10B41/27

CPC分类号： H01L29/78642 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/66431 ,  H01L29/6675 ,  H10B41/27

摘要： An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

公开(公告)号：US12119269B2

公开(公告)日：2024-10-15

申请号：US17824744

申请日：2022-05-25

申请人： Micron Technology, Inc.

发明人： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792 ,  H10B12/00 ,  H10B51/30 ,  H10B53/30 ,  H10B63/00 ,  H10B99/00 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823885 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/7926 ,  H10B12/395 ,  H10B51/30 ,  H10B53/30 ,  H10B63/34 ,  H10B99/00 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877

摘要： An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US20240339512A1

公开(公告)日：2024-10-10

申请号：US18747616

申请日：2024-06-19

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L29/417 ,  H01L29/10

CPC分类号： H01L29/41741 ,  H01L29/1037

摘要： A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.

公开(公告)号：US12087638B2

公开(公告)日：2024-09-10

申请号：US18334918

申请日：2023-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Yao Lin ,  Chih-Chung Chiu ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L21/823462 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66795 ,  H01L27/088

摘要： The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

公开(公告)号：US20240284652A1

公开(公告)日：2024-08-22

申请号：US18644874

申请日：2024-04-24

申请人： Intel Corporation

发明人： Peng ZHENG ,  Varun MISHRA ,  Tahir GHANI

IPC分类号： H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC分类号： H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545

摘要： Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US12062697B2

公开(公告)日：2024-08-13

申请号：US18055565

申请日：2022-11-15

申请人： Samsung Electronics Co., Ltd.

发明人： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC分类号： H01L29/10 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1037 ,  H01L21/02568 ,  H01L29/408 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/66795 ,  H01L29/785

摘要： Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20240266399A1

公开(公告)日：2024-08-08

申请号：US18636317

申请日：2024-04-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Georgios Vallianitis

IPC分类号： H01L29/10 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/1037 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66787 ,  H01L29/66969 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7869 ,  H01L29/78696

摘要： A transistor, an integrated semiconductor device, and methods of making the same are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

公开(公告)号：US20240266227A1

公开(公告)日：2024-08-08

申请号：US18165624

申请日：2023-02-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Liang Lu ,  Chang-Yin Chen ,  Jian-Hsuan Zheng ,  Che-Cheng Chang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/66545

摘要： A method of fabricating a semiconductor structure includes forming a semiconductor fin over a substrate. The method includes forming a semiconductor fin over a substrate. The method includes forming an isolation region around the semiconductor fin. The method includes forming a dummy gate structure over the semiconductor fin, which further includes performing a first etching process using a first etchant and subsequently performing a second etching process using a second etchant, where the first etchant is different from the second etchant in composition. The method includes forming source/drain features adjacent the dummy gate structure. The method includes replacing the dummy gate structure with a metal gate structure that is interposed between the source/drain features.

公开(公告)号：US12051722B2

公开(公告)日：2024-07-30

申请号：US18205671

申请日：2023-06-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sujin Jung ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC分类号： H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/1037 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US20240250173A1

公开(公告)日：2024-07-25

申请号：US18597813

申请日：2024-03-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiao-Chun CHANG ,  Guan-Jie SHEN

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/324 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.