-
公开(公告)号:US20190244971A1
公开(公告)日:2019-08-08
申请号:US16252301
申请日:2019-01-18
发明人: Eli Harari
IPC分类号: H01L27/11582 , H01L29/10 , H01L23/528 , H01L29/786 , H01L27/11573 , H01L27/1157 , G11C16/30 , G11C16/14 , H01L29/06 , H01L23/532 , H01L23/522 , H01L27/11565 , G11C16/04 , G11C16/26
CPC分类号: H01L27/11582 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/30 , H01L23/5226 , H01L23/528 , H01L23/53257 , H01L23/5329 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/0649 , H01L29/1037 , H01L29/78642
摘要: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.
-
公开(公告)号:US20190237367A1
公开(公告)日:2019-08-01
申请号:US16372717
申请日:2019-04-02
IPC分类号: H01L21/8238 , H01L21/225 , H01L21/28 , H01L21/308 , H01L21/768 , H01L27/11 , H01L29/16 , H01L29/51 , H01L29/49
CPC分类号: H01L21/823828 , H01L21/2018 , H01L21/2253 , H01L21/2255 , H01L21/2257 , H01L21/28088 , H01L21/28114 , H01L21/28123 , H01L21/28132 , H01L21/28518 , H01L21/28568 , H01L21/3086 , H01L21/31111 , H01L21/31116 , H01L21/76 , H01L21/764 , H01L21/76805 , H01L21/76829 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76877 , H01L21/76897 , H01L21/76898 , H01L21/8221 , H01L21/823418 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L21/823487 , H01L21/823807 , H01L21/823871 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53257 , H01L27/11 , H01L27/1104 , H01L29/04 , H01L29/0657 , H01L29/1037 , H01L29/16 , H01L29/401 , H01L29/41741 , H01L29/42356 , H01L29/42376 , H01L29/4238 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66666 , H01L29/66787 , H01L29/7827
摘要: The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.
-
公开(公告)号:US20190214397A1
公开(公告)日:2019-07-11
申请号:US16208072
申请日:2018-12-03
发明人: Leo Xing , Andy Liu , Xian Liu , Chunming Wang , Melvin Dao , Nhan Do
IPC分类号: H01L27/11521 , H01L29/423 , H01L29/08 , H01L29/10 , H01L23/532
CPC分类号: H01L27/11521 , H01L23/53295 , H01L29/0847 , H01L29/1037 , H01L29/42328 , H01L29/42336
摘要: A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.
-
公开(公告)号:US20190198520A1
公开(公告)日:2019-06-27
申请号:US15948639
申请日:2018-04-09
发明人: Changhan Kim , Chet E. Carter , Cole Smith , Collin Howder , Richard J. Hill , Jie Li
IPC分类号: H01L27/11582 , H01L29/10 , H01L23/528 , H01L27/11568 , H01L29/51 , H01L29/49 , H01L21/311 , H01L21/02 , H01L21/28 , H01L27/11521 , H01L27/11556 , H01L29/788 , H01L29/792 , H01L29/66
CPC分类号: H01L27/11582 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02255 , H01L21/02636 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L23/528 , H01L27/11521 , H01L27/11556 , H01L27/11568 , H01L29/1037 , H01L29/4991 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/7889 , H01L29/7926
摘要: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.
-
公开(公告)号:US20190067317A1
公开(公告)日:2019-02-28
申请号:US15913947
申请日:2018-03-07
发明人: Tomonari SHIODA , Junya FUJITA , Tatsuro NISHIMOTO , Yoshiaki FUKUZUMI , Atsushi FUKUMOTO , Hajime NAGANO
IPC分类号: H01L27/11582 , H01L27/11556 , H01L29/36 , H01L29/10 , H01L29/78
CPC分类号: H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L29/1037 , H01L29/1095 , H01L29/36 , H01L29/40117 , H01L29/7827 , H01L51/5259
摘要: According to one embodiment, the silicon layer includes phosphorus. The buried layer is provided on the silicon layer. The stacked body is provided on the buried layer. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and through the buried layer, and includes a sidewall portion positioned at a side of the buried layer. The silicon film is provided between the buried layer and the sidewall portion of the semiconductor body. The silicon film includes silicon as a major component and further includes at least one of germanium or carbon.
-
公开(公告)号:US20180374752A1
公开(公告)日:2018-12-27
申请号:US16119369
申请日:2018-08-31
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
发明人: Fei ZHOU
IPC分类号: H01L21/8234 , H01L29/66 , H01L29/10 , H01L29/06 , H01L27/088 , H01L21/02 , H01L21/762 , H01L27/11
CPC分类号: H01L21/823412 , H01L21/02236 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L27/1104 , H01L29/0653 , H01L29/1037 , H01L29/66818
摘要: Semiconductor structure is provided. An exemplary semiconductor structure includes a semiconductor substrate including fin structures. The fin structures include a plurality of first fin structures having a first width and a plurality of second fin structures. The second fin structure has a second width at a lower potion and a third width at an upper portion, and the second width is greater than each of the first width and the third width. The semiconductor structure includes a first isolation film formed on the semiconductor substrate and between adjacent fin structures. The first isolation film has a top surface lower than the fin structures. The upper portion of each second fin structure having the third width passes through the top surface of the first isolation film.
-
公开(公告)号:US20180358374A1
公开(公告)日:2018-12-13
申请号:US15868084
申请日:2018-01-11
发明人: Kwang Soo KIM , Hyun Suk KIM , Soon Hyuk HONG , Doo Hee HWANG
IPC分类号: H01L27/11582 , H01L29/423 , H01L29/10 , H01L23/532 , H01L23/528 , H01L27/11565 , H01L29/792
CPC分类号: H01L27/11582 , H01L23/5283 , H01L23/53271 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L29/1037 , H01L29/4234 , H01L29/7926
摘要: A vertical memory device includes a gate structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel structures penetrating through the gate structure and extending in a direction perpendicular to an upper surface of the substrate, a common source line penetrating the gate structure and extending in a first direction, a metal line extended above the common source line in the first direction, and a plurality of connection portions interposed between the metal line and the common source line.
-
公开(公告)号:US20180350939A1
公开(公告)日:2018-12-06
申请号:US16043588
申请日:2018-07-24
IPC分类号: H01L29/49 , H01L29/423 , H01L29/10 , H01L29/786 , H01L29/66 , H01L29/78 , H01L23/31 , H01L29/08 , H01L29/51 , C23C14/06 , C23C14/08 , C23C14/58 , C23C16/34 , C23C16/40 , C23C16/56 , H01L21/02 , H01L21/306 , H01L21/308 , H01L21/3105 , H01L21/321
CPC分类号: H01L29/4991 , C23C14/0652 , C23C14/081 , C23C14/083 , C23C14/588 , C23C16/345 , C23C16/401 , C23C16/56 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02189 , H01L21/02266 , H01L21/02271 , H01L21/30604 , H01L21/3081 , H01L21/31055 , H01L21/32115 , H01L23/315 , H01L29/0847 , H01L29/1037 , H01L29/42364 , H01L29/42392 , H01L29/517 , H01L29/6656 , H01L29/66666 , H01L29/7827 , H01L29/78642 , H01L29/78654 , H01L2029/42388
摘要: A transistor includes a channel fin. A gate stack is formed on sidewalls of the channel fin. A top spacer is formed over the gate stack. The top spacer includes dielectric material that fully encapsulates air gaps directly above the gate stack. A top source/drain region formed on the channel fin.
-
公开(公告)号:US20180350830A1
公开(公告)日:2018-12-06
申请号:US15816638
申请日:2017-11-17
申请人: YEONG DAE LIM , SEUNG JAE JUNG , JIN YOUNG BANG , IL WOO KIM , HO GIL JUNG
发明人: YEONG DAE LIM , SEUNG JAE JUNG , JIN YOUNG BANG , IL WOO KIM , HO GIL JUNG
IPC分类号: H01L27/11582 , H01L29/06 , H01L27/11568 , H01L29/10
CPC分类号: H01L27/11582 , H01L21/0217 , H01L21/02211 , H01L21/02271 , H01L21/0228 , H01L21/02532 , H01L21/02595 , H01L21/02636 , H01L21/28282 , H01L21/31111 , H01L27/11565 , H01L27/11568 , H01L29/0657 , H01L29/1037
摘要: A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.
-
公开(公告)号:US20180342615A1
公开(公告)日:2018-11-29
申请号:US15813523
申请日:2017-11-15
发明人: Marc A. Bergendahl , Kangguo Cheng , Gauri Karve , Fee Li Lie , Eric R. Miller , John R. Sporre , Sean Teehan
IPC分类号: H01L29/78 , H01L29/08 , H01L29/10 , H01L29/66 , H03K17/687 , H01L29/06 , H01L29/49 , H01L29/51
CPC分类号: H01L29/7827 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66666 , H01L29/785 , H01L29/78642 , H03K17/687
摘要: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
-
-
-
-
-
-
-
-
-