公开(公告)号：US5130580A

公开(公告)日：1992-07-14

申请号：US550997

申请日：1990-07-11

申请人： Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

发明人： Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise. The bias circuit is connected to a clamping circuit having a comparator circuit to clamp the active restore voltage of the sense amplifier driving circuit, so that the active restore voltage can be maintained at the level of an internal voltage (approximately 4V), thereby preventing the distortion of the characteristics of the cell device and eliminating the necessity of additional standby current by enabling the sense amplifier only for the active restore operation. Further, the sense amplifier driving circuit comprises a constant circuit including two or more current mirror circuits which are sequentially activated, whereby the sense amplifier driving signals are made to have stable linear dual slopes.

摘要翻译： 一种读出放大器驱动电路，用于通过接通/断开连接在外部电压Vcc端子和接地电压Vss端子之间的驱动晶体管来控制高密度半导体存储器件的读出放大器，包括：偏置电路，包括MOS晶体管，连接到 驱动MOS晶体管与其形成电流镜像电路，其由读出放大器使能时钟控制，并且具有MOS晶体管的恒定电流源，其中Vcc和Vss之间的中间电平的偏置电压被施加到其栅极端子。 偏置电路连接到驱动晶体管的栅极端子，以控制驱动晶体管的栅极电压，从而降低读出放大器驱动信号的峰值电流。 此外，在具有线性双斜率的波形中产生驱动信号，导致功率噪声的降低。 偏置电路连接到具有比较器电路的钳位电路，以钳位读出放大器驱动电路的有效恢复电压，使得有效恢复电压可以保持在内部电压（大约4V）的水平，从而防止 通过使感测放大器仅用于主动恢复操作，从而消除了电池装置特性的失真，并消除了额外待机电流的必要性。 此外，读出放大器驱动电路包括一个恒定电路，该恒定电路包括被依次激活的两个或多个电流镜电路，从而使读出放大器驱动信号具有稳定的线性双斜率。

公开(公告)号：US5034625A

公开(公告)日：1991-07-23

申请号：US417314

申请日：1989-10-05

申请人： Dong-sun Min ,  Hoon Choi

发明人： Dong-sun Min ,  Hoon Choi

IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/34 ,  G11C11/408 ,  H01L21/822 ,  H01L27/06 ,  H03K19/094

CPC分类号： G05F3/205

摘要： A semiconductor substrate bias circuit is disclosed which comprises: first and second substrate biasing means connected in parallel between the substrate and a ground node, for pumping the charges from said substrate to said ground node or in the reverse direction in order to bias said substrate; and a detecting means for selectively enabling said first and second substrate biasing means in accordance with the levels of the substrate bias voltage. The circuit of the present invention is capable of supplying adequate bias voltages depending on the various operating modes, reducing the standby current loss at a standby state, and is suitable for being installed on a VLSI semiconductor chip.

摘要翻译： 公开了一种半导体衬底偏置电路，其包括：第一和第二衬底偏置装置并联连接在衬底和接地节点之间，用于将电荷从所述衬底泵送到所述接地节点或反向，以偏置所述衬底; 以及检测装置，用于根据衬底偏置电压的电平有选择地使能所述第一和第二衬底偏置装置。 本发明的电路能够根据各种操作模式提供足够的偏置电压，从而在备用状态下降低待机电流损耗，并且适合于安装在VLSI半导体芯片上。