公开(公告)号：US07453833B2

公开(公告)日：2008-11-18

申请号：US10787671

申请日：2004-02-26

申请人： Doo-youll Yi ,  Kyung-wan Nam

发明人： Doo-youll Yi ,  Kyung-wan Nam

IPC分类号： H04B7/005

CPC分类号： H04L29/06 ,  H04L69/324 ,  H04W28/06 ,  H04W28/18 ,  H04W28/22 ,  H04W84/12

摘要： In a method and apparatus for data transmission suitable for a high-performance wireless LAN, the apparatus utilizes a serial communication interface device to perform data transmission between a master and a slave. The data transmission apparatus includes a data input unit for receiving at least one of transmission rate data and transmission length data to be transmitted from the master to the slave. A selection unit receives the at least one of the transmission rate data and the transmission length data from the data input unit, and receives at least one of a corresponding first event signal and a second event signal for selectively transmitting at least one of the transmission rate data and the transmission length data respectively to the slave. A controller receives the at least one of the transmission rate data and the transmission length data from the selection unit and controls a serial communication interface used to transmit the at least one of the transmission rate data and the transmission length data to the slave. A control unit automatically controls critical timing of the transmission of the at least one of the transmission rate data and the transmission length data, in response to activation of the corresponding at least one first event signal and second event signal.

摘要翻译： 在适用于高性能无线LAN的数据传输方法和装置中，该装置利用串行通信接口装置在主机与从机之间执行数据传输。 数据传输装置包括：数据输入单元，用于接收要从主设备发送到从设备的传输速率数据和传输长度数据中的至少一个。 选择单元从数据输入单元接收传输速率数据和传输长度数据中的至少一个，并且接收对应的第一事件信号和第二事件信号中的至少一个，用于选择性地发送传输速率 数据和传输长度数据分别到从机。 控制器从选择单元接收传输速率数据和传输长度数据中的至少一个，并控制用于将传输速率数据和传输长度数据中的至少一个发送到从设备的串行通信接口。 响应于对应的至少一个第一事件信号和第二事件信号的激活，控制单元自动控制传输速率数据和传输长度数据中的至少一个传输的关键定时。

公开(公告)号：US20060026330A1

公开(公告)日：2006-02-02

申请号：US11109556

申请日：2005-04-19

申请人： Doo-youll Yi ,  Hae-jin Song

发明人： Doo-youll Yi ,  Hae-jin Song

IPC分类号： G06F13/36

CPC分类号： G06F13/364 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151

摘要： A bus arbitration system includes a bus master, a bus arbitration circuit and a clock signal changing circuit. The bus master is configured to enter a power saving mode of operation in response to a disabled first master clock signal. The bus arbitration circuit is configured to issue a bus access grant to the first bus master in response to a request for bus access issued by the first bus master. The clock signal changing circuit is electrically coupled to the first bus master and the bus arbitration circuit. The clock signal changing circuit is configured to generate the disabled first master clock signal in response to the request for bus access. The clock signal changing circuit is further configured to convert the disabled first master clock signal to an enabled first master clock signal in response to the bus access grant.

摘要翻译： 总线仲裁系统包括总线主机，总线仲裁电路和时钟信号改变电路。 总线主机被配置为响应于禁用的第一主时钟信号而进入功率节省模式。 总线仲裁电路被配置为响应于由第一总线主控器发出的对总线访问的请求而向第一总线主控器发出总线访问许可。 时钟信号改变电路电耦合到第一总线主机和总线仲裁电路。 时钟信号改变电路被配置为响应于对总线访问的请求而产生禁用的第一主时钟信号。 时钟信号改变电路还被配置为响应于总线访问许可将禁用的第一主时钟信号转换为启用的第一主时钟信号。