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1.发明授权Method of stabilizing component and net names of integrated circuits in electronic design automation systems 失效稳定电子设计自动化系统中集成电路的组件和网络名称的方法
公开(公告)号：US5805861A
公开(公告)日：1998-09-08
申请号：US524017
申请日：1995-08-29
CPC分类号： G06F17/5045
摘要： A method used by an electronic design automation system for stabilizing the names of components and nets of an integrated circuit from one design version to another. A previous integrated circuit design version and a current integrated circuit design version are partitioned into multiple cones of logic design. Each cone of logic design is defined by a path from a logic designer-defined apex net to a logic designer-defined base net affecting the apex net. Selected cones of logic design are compared. If the selected cones have identical logical structure, the component and net names of the previous integrated circuit design version are transferred to the current integrated circuit design version. If the selected cones of logic design do not have identical structure, then the component and net names for subsections of the selected cones of logic design that do have identical logical structure are transferred to the current integrated circuit design version, and new component and net names are assigned to those subsections of the selected cones of logic design from the current integrated circuit design version which did not exist in the previous integrated circuit design version.
摘要翻译： 电子设计自动化系统使用的方法，用于将集成电路的组件和网络的名称从一个设计版本稳定到另一个。 以前的集成电路设计版本和当前的集成电路设计版本分为多个逻辑设计锥。 逻辑设计的每一个锥体由一个从逻辑设计者定义的顶点网络到影响顶点网络的逻辑设计者定义的基准网络的路径来定义。 选择的逻辑设计锥被比较。 如果选择的锥体具有相同的逻辑结构，则先前集成电路设计版本的组件和网络名称将转移到当前的集成电路设计版本。 如果所选择的逻辑设计锥不具有相同的结构，那么确定具有相同逻辑结构的所选择的逻辑设计锥的部分和网名被转移到当前的集成电路设计版本，并且新的组件和网名 被分配到从先前的集成电路设计版本中不存在的当前集成电路设计版本中选择的逻辑设计锥的那些子部分。
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2.发明授权Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints 失效使用四态模拟器测试具有可变时序约束的集成电路设计的方法
公开(公告)号：US5819072A
公开(公告)日：1998-10-06
申请号：US671432
申请日：1996-06-27
CPC分类号： G06F17/5031
摘要： Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.
摘要翻译： 对于对于多个并行路径具有不同时序约束的电路设计执行关键路径时序分析的方法。 方法包括清除电路设计的状态，将电路设计中的控制线设置为所选择的一组控制信号，以及通过使用所选择的一组控制来模拟电路设计来识别要标记的时序分析的电路设计的阻塞网 信号作为输入信号。 识别的阻塞点被添加到标识要分析的电路设计中的路径的列表。 处理所有可能的控制信号组。 然后使用列表作为输入数据对电路设计进行时序分析。 关键的一步是识别阻塞点。 针对具有未知值的电路设计中的栅极的每个净输入识别阻塞点，以及针对所选择的一组控制信号的来自栅极的输出网上的已知值。 输入到定时分析工具的阻塞点确保在关键路径时序分析期间对这些网络进行分析，因此检测到电路设计中的所有可能的定时违规。
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3.发明授权Method and apparatus for optimizing a circuit design having multi-paths therein 失效用于优化其中具有多路径的电路设计的方法和设备
公开(公告)号：US5956256A
公开(公告)日：1999-09-21
申请号：US752618
申请日：1996-11-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.
摘要翻译： 一种用于优化其中具有多循环路径的电路设计的方法和装置。 在示例性实施例中，可以通过以下方式来优化具有多个循环路径的电路设计：识别电路设计内的多个循环路径中的至少一个，以及识别与之相关联的对应的限定时钟; 用替换时钟替换相应时钟中选定的时钟; 并使用更换时钟优化电路设计。 通过使用具有等于相应时钟的时钟周期的替换时钟，通常是合格的时钟，标准优化工具可以正确优化电路设计。
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4.发明授权Method and apparatus for associating selected circuit instances and for performing a group operation thereon 失效用于关联所选择的电路实例并用于在其上执行组操作的方法和装置公开(公告)号：US06910200B1
公开(公告)日：2005-06-21
申请号：US08789028
申请日：1997-01-27
CPC分类号： G06F17/505
摘要： A method and apparatus for associating selected circuit instances, and for allowing a later group manipulation thereof. Prior to entering a database editor tool, selected instances may be associated with one another, and the association may be recorded in the circuit design database. The database editor tool may then read the circuit design database and identify the selected instances and the association therebetween. The associated instances may be called a group, or preferably a stack. The database editor tool may then perform a group operation on the instances associated with the stack.
摘要翻译： 一种用于关联所选择的电路实例并且用于允许稍后的组操作的方法和装置。 在输入数据库编辑器工具之前，所选择的实例可以彼此关联，并且关联可以被记录在电路设计数据库中。 然后，数据库编辑器工具可以读取电路设计数据库并识别所选择的实例及其间的关联。 相关联的实例可以被称为组，或者优选地称为堆栈。 然后，数据库编辑器工具可以对与堆栈相关联的实例执行组操作。
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5.发明授权Method and apparatus for using a placement tool to manipulate cell substitution lists 失效使用放置工具来操纵细胞置换列表的方法和装置公开(公告)号：US06701289B1
公开(公告)日：2004-03-02
申请号：US08789029
申请日：1997-01-27
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06F17/505
摘要： A placement tool that may import and export cell substitution and/or cell selection lists. The cell substitution and/or cell selection lists may be used by the placement tool to substitute and/or modify the placement design database, rather than the original schematic or behavioral database. This may eliminate the need to re-synthesize the circuit design during each design iteration. The present invention further contemplates providing a reset feature which may reset the circuit design database to a previous state, if desired.
摘要翻译： 可以导入和导出单元格替换和/或单元格选择列表的布局工具。 细胞替换和/或细胞选择列表可以被放置工具用于替代和/或修改放置设计数据库，而不是原始原理图或行为数据库。 这可能会消除在每次设计迭代期间重新合成电路设计的需要。 本发明还考虑提供复位特征，如果需要，可以将电路设计数据库重置为先前状态。
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6.发明授权Method and apparatus for efficiently viewing a number of selected components using a database editor tool 失效使用数据库编辑器工具有效地查看多个所选择的组件的方法和装置公开(公告)号：US07076410B1
公开(公告)日：2006-07-11
申请号：US08789025
申请日：1997-01-27
申请人： Joseph P. Kerzman , James E. Rezek
发明人： Joseph P. Kerzman , James E. Rezek
CPC分类号： G06F17/5045
摘要： A method and apparatus for efficiently viewing selected cells using a database editor tool. By using a cell selection list that identifies a number of selected components, the present invention may allow the user to sequentially view the selected components by using a number of pre-defined “hot-keys”. In addition, the present invention may automatically set the design hierarchy in the database editor tool to an appropriate level so that the component being viewed can be easily manipulated by the circuit designer.
摘要翻译： 一种使用数据库编辑器工具有效地查看所选单元的方法和装置。 通过使用识别多个所选择的组件的小区选择列表，本发明可以允许用户通过使用多个预定义的“热键”来顺序地查看所选择的组件。 此外，本发明可以将数据库编辑器工具中的设计层次自动设置到适当的水平，使得被查看的组件可以容易地被电路设计者操纵。
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7.发明授权Method for placing logic functions and cells in a logic design using floor planning by analogy 失效将逻辑功能和单元格放置在使用楼层规划的逻辑设计中的方法
公开(公告)号：US5696693A
公开(公告)日：1997-12-09
申请号：US414881
申请日：1995-03-31
申请人： Mark D. Aubel , Arthur F. Boehm , Joseph P. Kerzman , James E. Rezek , John T. Rusterholz , Richard F. Paul
发明人： Mark D. Aubel , Arthur F. Boehm , Joseph P. Kerzman , James E. Rezek , John T. Rusterholz , Richard F. Paul
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes. The size of the sets of selected logic functions and cells may be arbitrarily large, thereby providing advantages over simple manual placement of logic functions and cells in a floor plan.
摘要翻译： 计算机辅助设计系统用于将逻辑功能和单元放置在大规模集成电路芯片的平面图中的方法。 一组选定的逻辑功能和要放置的单元的结构与先前已经放置在平面图中的一组选定的逻辑功能和单元进行比较。 如果单元的数量和组的结构是类似的，则所选择的逻辑功能和要放置的单元基于所选择的逻辑功能和已经被存储的单元的物理位置和结构自动地在平面图中分配物理位置 放置，并在定向模式。 取向模式提供了所选逻辑功能和单元格围绕水平轴，垂直轴或水平轴和垂直轴的位置的反射。 所选择的逻辑功能和单元组的大小可以是任意大的，从而提供了优于在平面图中简单地手动放置逻辑功能和单元的优点。
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8.发明授权Method and apparatus for selecting components within a circuit design database 失效用于在电路设计数据库中选择组件的方法和装置公开(公告)号：US06684376B1
公开(公告)日：2004-01-27
申请号：US08789026
申请日：1997-01-27
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method and apparatus for efficiently selecting cells within a circuit design database. The invention includes four primary features for selecting cells including (1) selecting only those cells that are in a pre-identified region and within a pre-identified selection area; (2) maneuvering through the circuit design hierarchy and selecting cells or regions at selected levels of hierarchy by using predetermined up and down hot-keys; (3) sorting selected cells by instance name, and manually selecting a desired cell or region from the resulting sorted list; and (4) sorting selected cells by a corresponding net name, and manually selecting a desired cell or region from the resulting sorted list.
摘要翻译： 一种用于有效地选择电路设计数据库内的单元的方法和装置。 本发明包括用于选择单元的四个主要特征，包括：（1）仅选择在预先识别的区域内和预先识别的选择区域内的那些单元; （2）通过电路设计层次来操纵，并通过使用预定的上下热键选择所选层级的单元或区域; （3）按实例名称对所选择的单元进行排序，并从所得到的排序列表中手动选择所需单元格或区域; 和（4）通过相应的网络名称对所选择的单元格进行排序，并从所得到的排序列表中手动选择所需的单元格或区域。
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9.发明授权Method and apparatus for selectively viewing nets within a database editor tool 失效用于在数据库编辑器工具内选择性地查看网络的方法和装置公开(公告)号：US06516456B1
公开(公告)日：2003-02-04
申请号：US08789027
申请日：1997-01-27
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5045
摘要： A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or received by the selected objects. In a preferred embodiment, the number of objects are placed objects within a placement tool. Second, for those nets that are selected, and that are also coupled to un-placed cells, the present invention contemplate providing fly-wires from the corresponding selected objects to a predetermined location representative of an approximate expected location for the un-placed cells. Third, the present invention contemplate providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed. Finally, the fourth feature of the present invention contemplates providing a means for selectively viewing only those nets that cross a predetermined hierarchical boundary within the circuit design database.
摘要翻译： 一种用于在数据库编辑器工具内选择性地查看网络的方法和装置。 本发明提供了用于选择性地观察网络的四个主要特征。 首先，本发明考虑了选择多个对象，并且仅查看那些从所选择的对象中驱动或接收的网络。 在优选实施例中，物体的数量被放置在放置工具内。 第二，对于所选择的并且还耦合到未放置的单元的网络，本发明考虑将来自相应的所选对象的飞线提供到表示未放置的单元的近似预期位置的预定位置。 第三，本发明考虑提供一种矢量滤波器，其可以仅允许观看具有所选总线宽度范围的矢量网。 最后，本发明的第四特征设想提供一种用于仅选择性地观察跨越电路设计数据库内的预定分层边界的那些网络的装置。
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10.发明授权Method and apparatus for distributing a clock tree within a hierarchical circuit design 失效在分层电路设计中分配时钟树的方法和装置
公开(公告)号：US5912820A
公开(公告)日：1999-06-15
申请号：US786851
申请日：1997-01-22
CPC分类号： G06F17/5077 , G06F1/10
摘要： A method and apparatus for distributing clock drivers within a hierarchical circuit design, wherein the clock drivers are concentrated in locations where they are actually needed rather than uniformly distributed throughout the circuit design. In an exemplary embodiment, the actual clock loads within a selected hierarchical region are determined, and a sufficient number of clock drivers are added as children objects to the selected hierarchical region. Since many placement tools may place the children objects within an outer boundary of the corresponding parent object, the clock drivers, as children objects of the selected hierarchical region, may be placed within the outer boundary of the selected hierarchical region. Accordingly, the clock drivers may be concentrated in the locations where actually needed.
摘要翻译： 一种用于在分层电路设计中分配时钟驱动器的方法和装置，其中时钟驱动器集中在实际需要的位置，而不是整个电路设计中均匀分布。 在示例性实施例中，确定所选分层区域内的实际时钟负载，并且将足够数量的时钟驱动器作为子对象添加到所选择的分层区域。 由于许多放置工具可以将子对象放置在对应的父对象的外边界内，作为所选分层区域的子对象的时钟驱动器可以被放置在所选分层区域的外边界内。 因此，时钟驱动器可能集中在实际需要的位置。
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