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1.发明授权Method and apparatus for optimizing a circuit design having multi-paths therein 失效用于优化其中具有多路径的电路设计的方法和设备
公开(公告)号：US5956256A
公开(公告)日：1999-09-21
申请号：US752618
申请日：1996-11-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.
摘要翻译： 一种用于优化其中具有多循环路径的电路设计的方法和装置。 在示例性实施例中，可以通过以下方式来优化具有多个循环路径的电路设计：识别电路设计内的多个循环路径中的至少一个，以及识别与之相关联的对应的限定时钟; 用替换时钟替换相应时钟中选定的时钟; 并使用更换时钟优化电路设计。 通过使用具有等于相应时钟的时钟周期的替换时钟，通常是合格的时钟，标准优化工具可以正确优化电路设计。
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2.发明授权Method and apparatus for optimizing a gated clock structure using a standard optimization tool 失效使用标准优化工具优化门控时钟结构的方法和装置
公开(公告)号：US5980092A
公开(公告)日：1999-11-09
申请号：US752620
申请日：1996-11-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.
摘要翻译： 一种使用优化工具来优化使用门控时钟结构的设计的方法和装置。 简而言之，本发明允许标准优化器工具确定到达逻辑门的两个或多个信号的相对定时，其中逻辑门形成门控时钟信号。 通常，标准优化器工具只能检查到达存储元件的两个或多个信号之间的相对时序。 根据本发明，所选择的逻辑门可以被建模为存储元件。 因此，可以使用标准优化器工具来正确地优化使用门控时钟结构的设计，并且特别地，正确地优化提供时钟的逻辑并使能信号到时钟门控元件。
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3.发明授权Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool 失效使用标准优化工具在电路设计中识别门控时钟的方法和装置
公开(公告)号：US5864487A
公开(公告)日：1999-01-26
申请号：US752616
申请日：1996-11-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus for identifying gated clocks within a circuit design. In a typical design, each of the number of gated clock signals is uniquely determined by a particular logical combination of a number of raw clock signals and a number of enable signals. In the present invention, the gated clock signals may be identified by: identifying which of the number of raw clock signals is coupled, through combinational logic, to a selected one of the number of state devices, thereby resulting in an identified raw clock signal; identifying which of the number of enable signals is coupled, through combinational logic, to the selected one of the number of state devices, thereby resulting in an identified enable signal; and determining which of the number of gated clock signals is uniquely determined by the particular combination of the identified raw clock signal and the identified enable signal.
摘要翻译： 一种用于在电路设计中识别门控时钟的方法和装置。 在典型的设计中，多个门控时钟信号中的每一个由多个原始时钟信号和多个使能信号的特定逻辑组合唯一地确定。 在本发明中，门控时钟信号可以通过以下方式来识别：将多个原始时钟信号中的哪一个通过组合逻辑耦合到多个状态设备中的所选择的一个，由此导致所识别的原始时钟信号; 通过组合逻辑将所述使能信号的数量中的哪一个耦合到所述多个状态设备中的所选择的一个，从而导致所识别的使能信号; 并且通过所识别的原始时钟信号和所识别的使能信号的特定组合来确定门控时钟信号数量中的哪一个唯一地确定。
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4.发明申请System and Method for Detecting and Recovering from Errors in an Instruction Stream of an Electronic Data Processing System 审中-公开在电子数据处理系统的指令流中检测和恢复错误的系统和方法公开(公告)号：US20100131796A1
公开(公告)日：2010-05-27
申请号：US12641014
申请日：2009-12-17
CPC分类号： G06F11/0793 , G06F9/30145 , G06F9/3802 , G06F9/3812 , G06F9/3824 , G06F9/3836 , G06F9/3865 , G06F9/3867 , G06F9/3873 , G06F11/0721 , G06F11/1064 , G06F12/0802
摘要： A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.
摘要翻译： 提供了一种系统和方法，用于检测和恢复电子数据处理系统的指令高速缓存RAM和/或操作数高速缓存RAM中的错误。 在某些情况下，指令高速缓存RAM和/或操作数缓存RAM中的错误从数据处理系统的操作系统的任何必需的交互中被检测和恢复。 因此，在许多情况下，指令高速缓存RAM和/或操作数高速缓存RAM中的错误可以无缝和高效地处理，而不需要专门的操作系统程序，或者在某些情况下，维护技术人员帮助诊断和/或修复 错误。
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5.发明授权Method and apparatus for performing drive strength adjust optimization in a circuit design 失效在电路设计中执行驱动强度调整优化的方法和装置
公开(公告)号：US5724250A
公开(公告)日：1998-03-03
申请号：US598506
申请日：1996-02-07
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method and apparatus for efficiently optimizing a circuit design by substituting identified cells within the circuit design with logically equivalent cells having different drive strengths. The present invention eliminates the need to update the design database and to place and route the circuit design during each design iteration. Rather, an improved extraction tool is provided which incorporates a cell substitution list, and updates the RC file therefrom. The updated RC file is used by the timing analysis tool to determine if the updated design will meet the design specification. After the design meets the design specification, a final place and route may be performed.
摘要翻译： 一种用于通过用具有不同驱动强度的逻辑等效单元替换电路设计内的所识别的单元来有效优化电路设计的方法和装置。 本发明消除了在每次设计迭代期间更新设计数据库和放置和布线电路设计的需要。 相反，提供了一种改进的提取工具，其包括单元替换列表，并从其更新RC文件。 更新的RC文件由时序分析工具用于确定更新后的设计是否符合设计规范。 在设计符合设计规范之后，可以执行最终的位置和路线。
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6.发明授权Method and apparatus for increasing computer performance through asynchronous memory block initialization 有权通过异步存储器块初始化提高计算机性能的方法和装置公开(公告)号：US06601153B1
公开(公告)日：2003-07-29
申请号：US09476022
申请日：1999-12-31
IPC分类号： G06F9312
CPC分类号： G06F12/08 , G06F12/0891 , Y10S707/99953
摘要： A system and method for increasing processing performance in a computer system by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, such as processing stalls and idle memory write periods. The inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles. Addresses corresponding to those initialized data blocks are then made available to the computing system to facilitate use of the data blocks.
摘要翻译： 一种通过在非活动存储器访问期间异步执行不与正常指令处理冲突的系统活动来提高计算机系统中的处理性能的系统和方法。 计算机系统包括处理指令流的指令的至少一个指令处理器和存储数据的存储器。 识别存储器中的一个或多个非活动数据块，并且生成与所识别的非活动数据块相对应的地址列表。 识别在计算机系统中处理期间发生的可用计算周期，例如处理停顿和空闲存储器写入周期。 在可用的计算周期期间将与地址列表相关联的非活动数据块初始化为预定状态。 然后使与这些初始化的数据块相对应的地址可用于计算系统以便于使用数据块。
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公开(公告)号：US5867699A
公开(公告)日：1999-02-02
申请号：US686258
申请日：1996-07-25
CPC分类号： G06F9/382 , G06F9/264 , G06F9/30054 , G06F9/3804
摘要： Method and apparatus for changing the sequential execution of instructions in a pipelined instruction processor by using a microcode controlled redirect controller. The execution of a redirect instruction by the pipelined instruction processor provides a number of microcode bits including a target address to the redirect controller, a predetermined combination of the microcode bits then causes the redirect controller to redirect the execution sequence of the instructions from the next sequential instruction to a target instruction.
摘要翻译： 用于通过使用微码控制的重定向控制器来改变流水线指令处理器中的指令的顺序执行的方法和装置。 由流水线指令处理器执行重定向指令向重定向控制器提供包括目标地址的多个微代码位，微代码位的预定组合然后使重定向控制器将指令的执行顺序从下一个顺序 指令到目标指令。
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8.发明授权System and method for detecting and recovering from errors in an instruction stream of an electronic data processing system 有权用于检测和从电子数据处理系统的指令流中的错误中恢复的系统和方法公开(公告)号：US07673190B1
公开(公告)日：2010-03-02
申请号：US11226803
申请日：2005-09-14
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/30145 , G06F9/3802 , G06F9/3812 , G06F9/3824 , G06F9/3836 , G06F9/3865 , G06F9/3867 , G06F9/3873 , G06F11/0721 , G06F11/1064 , G06F12/0802
摘要： A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.
摘要翻译： 提供了一种系统和方法，用于检测和恢复电子数据处理系统的指令高速缓存RAM和/或操作数高速缓存RAM中的错误。 在某些情况下，指令高速缓存RAM和/或操作数缓存RAM中的错误从数据处理系统的操作系统的任何必需的交互中被检测和恢复。 因此，在许多情况下，指令高速缓存RAM和/或操作数高速缓存RAM中的错误可以无缝和高效地处理，而不需要专门的操作系统程序，或者在某些情况下，维护技术人员帮助诊断和/或修复 错误。
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公开(公告)号：US4376976A
公开(公告)日：1983-03-15
申请号：US174035
申请日：1980-07-31
CPC分类号： G06F9/28
摘要： A system for overlapping macro instruction execution is described for use in a data processing system. A pair of control storage devices each store the micro instruction sets required to execute all macro instructions in the repertoire and are used for alternate macro instructions. Each of the controlled storage devices is addressable to entry addresses by the macro instructions. After entry, addressing is by the contents of the micro instructions with provision made for conditional branching. An overlap count storage device is provided for storing overlap counts for all possible sequences of macro instructions. These overlap counts define the number of micro instructions of the current macro instruction that must be executed before the next macro instruction can proceed. Micro instruction execution is by clock cycle and are counted as they are executed. The count is compared to the stored overlap count for the current sequence of macro instructions and overlap execution is enabled when comparison is found. Overlap of macro instruction execution is allowed to occur when the current remaining micro instructions for the current macro instruction define functions that are mutually exclusive with the functions controlled by the next macro instruction. During overlap, micro instructions are loaded in an execution register from both control storage devices. Overlapping instructions that have variable execution sequences is controlled by halting the count of micro instruction executions until the variable sequence has been completed.
摘要翻译： 描述用于重叠宏指令执行的系统用于数据处理系统。 一对控制存储设备每个存储执行所有所有宏指令所需的微指令集，并用于备用宏指令。 每个受控存储设备可通过宏指令对入口地址进行寻址。 进入后，通过微指令的内容进行寻址，并提供条件分支。 提供重叠计数存储装置用于存储所有可能的宏指令序列的重叠计数。 这些重叠计数定义了在下一个宏指令可以进行之前必须执行的当前宏指令的微指令数。 微指令执行是按时钟周期进行的，并在执行时进行计数。 将计数与当前宏指令序列的存储重叠计数进行比较，并且在发现比较时启用重叠执行。 当当前宏指令的当前剩余微指令定义与下一个宏指令控制的功能相互排斥的功能时，允许执行宏指令执行重叠。 在重叠期间，微指令从两个控制存储设备加载到执行寄存器中。 具有可变执行序列的重叠指令通过停止微指令执行的计数直到变量序列完成为止来控制。
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10.发明授权System and method for detecting and recovering from errors in a control store of an electronic data processing system 有权用于检测和从电子数据处理系统的控制存储器中的错误中恢复的系统和方法公开(公告)号：US07562263B1
公开(公告)日：2009-07-14
申请号：US11226499
申请日：2005-09-14
IPC分类号： G01F11/00
CPC分类号： G06F11/10
摘要： A system and method are provided for detecting and recovering from errors in a control store memory of an electronic data processing system. In some cases, errors in the control store memory are detected and recovered from without any required interaction with an operating system of the data processing system. Thus, errors in the control store memory can be handled seamlessly and efficiently, without requiring a maintenance technician, or in some cases, a specialized operating system routine, to help diagnose and fix the error.
摘要翻译： 提供了一种用于检测和从电子数据处理系统的控制存储器中的错误中恢复的系统和方法。 在某些情况下，控制存储存储器中的错误被检测和恢复，而不需要与数据处理系统的操作系统进行所需的交互。 因此，无需维护技术人员，或在某些情况下，专门的操作系统例程，可以无缝和高效地处理控制存储器中的错误，以帮助诊断和修复错误。
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