公开(公告)号：US6130138A

公开(公告)日：2000-10-10

申请号：US947948

申请日：1997-10-09

申请人： Hee-Seon Oh

发明人： Hee-Seon Oh

IPC分类号： H01L23/52 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/822 ,  H01L27/04 ,  H02L21/70

CPC分类号： H01L28/40

摘要： A method of making a semiconductor device having a thin film resistor, the method comprising the steps of: forming a first polysilicon layer on an upper surface of a field oxide layer formed on a semiconductor substrate; forming a first dielectric layer on a resultant material; ion-implanting an impurity for forming a resistor in the first polysilicon layer through the first dielectric layer; forming a second dielectric layer on an upper surface of the first dielectric layer; selectively etching the first and second dielectric layers and the first polysilicon layer to form a resistor poly (RPOLY) lower electrode; forming a second polysilicon layer on an upper surface of a resultant material; and forming a gate poly (GPOLY) by selectively etching the second polysilicon layer.

摘要翻译： 一种制造具有薄膜电阻器的半导体器件的方法，所述方法包括以下步骤：在形成在半导体衬底上的场氧化物层的上表面上形成第一多晶硅层; 在所得材料上形成第一介电层; 在所述第一多晶硅层中通过所述第一介电层离子注入用于形成电阻器的杂质; 在所述第一电介质层的上表面上形成第二电介质层; 选择性地蚀刻第一和第二介电层和第一多晶硅层以形成电阻器聚（RPOLY）下电极; 在所得材料的上表面上形成第二多晶硅层; 以及通过选择性蚀刻第二多晶硅层形成栅极聚（GPOLY）。

公开(公告)号：US5805861A

公开(公告)日：1998-09-08

申请号：US524017

申请日：1995-08-29

申请人： Douglas J. Gilbert ,  James E. Rezek ,  Harold E. Reindel ,  Allen B. A. Tabbert

发明人： Douglas J. Gilbert ,  James E. Rezek ,  Harold E. Reindel ,  Allen B. A. Tabbert

IPC分类号： G06F17/50 ,  H02L21/70

CPC分类号： G06F17/5045

摘要： A method used by an electronic design automation system for stabilizing the names of components and nets of an integrated circuit from one design version to another. A previous integrated circuit design version and a current integrated circuit design version are partitioned into multiple cones of logic design. Each cone of logic design is defined by a path from a logic designer-defined apex net to a logic designer-defined base net affecting the apex net. Selected cones of logic design are compared. If the selected cones have identical logical structure, the component and net names of the previous integrated circuit design version are transferred to the current integrated circuit design version. If the selected cones of logic design do not have identical structure, then the component and net names for subsections of the selected cones of logic design that do have identical logical structure are transferred to the current integrated circuit design version, and new component and net names are assigned to those subsections of the selected cones of logic design from the current integrated circuit design version which did not exist in the previous integrated circuit design version.

摘要翻译： 电子设计自动化系统使用的方法，用于将集成电路的组件和网络的名称从一个设计版本稳定到另一个。 以前的集成电路设计版本和当前的集成电路设计版本分为多个逻辑设计锥。 逻辑设计的每一个锥体由一个从逻辑设计者定义的顶点网络到影响顶点网络的逻辑设计者定义的基准网络的路径来定义。 选择的逻辑设计锥被比较。 如果选择的锥体具有相同的逻辑结构，则先前集成电路设计版本的组件和网络名称将转移到当前的集成电路设计版本。 如果所选择的逻辑设计锥不具有相同的结构，那么确定具有相同逻辑结构的所选择的逻辑设计锥的部分和网名被转移到当前的集成电路设计版本，并且新的组件和网名 被分配到从先前的集成电路设计版本中不存在的当前集成电路设计版本中选择的逻辑设计锥的那些子部分。