公开(公告)号：US5640114A

公开(公告)日：1997-06-17

申请号：US578101

申请日：1995-12-27

申请人： Yacoub M. El-Ziq ,  Douglas Kay

发明人： Yacoub M. El-Ziq ,  Douglas Kay

IPC分类号： H03K3/037 ,  H03K3/289

CPC分类号： H03K3/0375

摘要： A scan flip-flop includes a data input, a scan input, a mode selection input, a mode control input and a clock input. When the mode selection input is set to a first selection value, and the mode control input is set to a first control value, the scan flip-flop operates as a D flip-flop. When the mode selection input is set to a second selection value, the scan flip-flop shifts in a scan input value on the scan input when one of the mode control input and the clock input is toggled. Also, as long as the mode selection input is set to the first selection value, and the mode control input is set to a second control value, the scan flip-flop holds a current value within the scan flip-flop.

摘要翻译： 扫描触发器包括数据输入，扫描输入，模式选择输入，模式控制输入和时钟输入。 当模式选择输入被设置为第一选择值，并且模式控制输入被设置为第一控制值时，扫描触发器用作D触发器。 当模式选择输入被设置为第二选择值时，当切换模式控制输入和时钟输入之一时，扫描触发器在扫描输入上移动扫描输入值。 此外，只要模式选择输入被设置为第一选择值，并且模式控制输入被设置为第二控制值，则扫描触发器保持扫描触发器内的电流值。

公开(公告)号：US5938782A

公开(公告)日：1999-08-17

申请号：US719149

申请日：1996-09-24

申请人： Douglas Kay

发明人： Douglas Kay

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318541

摘要： A scan data flip-flop having improved timing characteristics is provided. A scan flip-flop includes: a first data input coupled with a first latch; a second data input coupled with said first latch; a clock input coupled with said first latch; a data control input; and a data controller operably coupled with said clock input and said data control input and said first latch; said data controller being configured to generate an enable signal responsive to a clock signal from said clock input and a data control signal from said data control input, and said enable signal to control the input of data into said first latch. The normal or first data input signal is preferably directly applied to the first latch within the scan data flip-flop according to the present invention. The data controller of the scan data flip-flop according to the present invention is preferably void of a multiplexer. A method for controlling the entry of data into a scan data flip-flop is also provided.

摘要翻译： 提供了具有改进的定时特性的扫描数据触发器。 扫描触发器包括：与第一锁存器耦合的第一数据输入; 与所述第一锁存器耦合的第二数据输入; 与所述第一锁存器耦合的时钟输入; 数据控制输入; 以及可操作地与所述时钟输入和所述数据控制输入和所述第一锁存器耦合的数据控制器; 所述数据控制器被配置为响应于来自所述时钟输入的时钟信号和来自所述数据控制输入的数据控制信号产生使能信号，并且所述使能信号控制数据输入到所述第一锁存器。 根据本发明，正常或第一数据输入信号优选地直接施加到扫描数据触发器内的第一锁存器。 根据本发明的扫描数据触发器的数据控制器优选地是多路复用器。 还提供了一种用于控制将数据输入扫描数据触发器的方法。

公开(公告)号：US4951278A

公开(公告)日：1990-08-21

申请号：US238581

申请日：1988-08-31

申请人： Jeffrey Biber ,  Jeffrey Cohen ,  John Holmbald ,  Zon-Hong Hsieh ,  Douglas Kay ,  Roy Spitzer

发明人： Jeffrey Biber ,  Jeffrey Cohen ,  John Holmbald ,  Zon-Hong Hsieh ,  Douglas Kay ,  Roy Spitzer

IPC分类号： H04L29/06

CPC分类号： H04L29/06

摘要： A data communications system has a layered communication architecture including network services protocols including a link layer and higher level protocols, and has IBM or IBM-compatible synchronous data link control (SDLC) devices including a host computer and a plurality of end user devices desiring to communicate across an X.25 packet-switching network (PSN) of the communications system. A packet assembler/disassembler (PAD) support X.25 communication across the PSN between the SDLC-utilizing host computer and the SDLC-utilizing end user device. In one embodiment, separate high level data link control (HDLC) PADs are provided at each end of the PSN operationally associated with the host computer and the plurality of end user devices, respectively. The PADS generate and respond to at least three formats of SDLC commands and responses, and, in association with their respective SDLC devices, perform at least four functions including a call setup phase, a data transfer phase, a call clearing phase, and handling of abnormal conditions. PAD means comprises qualified logical link control (QLLC) PAD means located at an end of said packet switching network for either operational association with said host computer or operational association with said plurality of end user devices. In another embodiment, a single qualified logical link control (QLLC) PAD performs functions similar to those of the HDLC PAD embodiment, except that rather than having a PAD at both ends (host end and terminal end) of a connection, a PAD is provided at only one end of the connection.

摘要翻译： 数据通信系统具有包括包括链路层和更高级别协议的网络服务协议的分层通信体系结构，并且具有IBM或IBM兼容的同步数据链路控制（SDLC）设备，包括主计算机和多个最终用户设备 通信通信系统的X.25分组交换网络（PSN）。 分组汇编器/分解器（PAD）支持在SDLC利用主机与使用SDLC的最终用户设备之间的PSN上的X.25通信。 在一个实施例中，分别在与主计算机和多个终端用户设备相关联的PSN的每一端分别提供单独的高级数据链路控制（HDLC）PAD。 PADS产生并响应至少三种格式的SDLC命令和响应，并且与其各自的SDLC设备相关联地执行至少四个功能，包括呼叫建立阶段，数据传送阶段，呼叫清除阶段以及处理 异常情况。 PAD装置包括位于所述分组交换网络的末端的合格逻辑链路控制（QLLC）PAD装置，用于与所述主机计算机的操作关联或与所述多个终端用户设备的操作关联。 在另一个实施例中，单个限定逻辑链路控制（QLLC）PAD执行与HDLC PAD实施例类似的功能，除了不是在连接的两端（主机端和终端）处具有PAD，而是提供PAD 在连接的一端。