公开(公告)号：US07703054B2

公开(公告)日：2010-04-20

申请号：US11697869

申请日：2007-04-09

申请人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

发明人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

IPC分类号： G06F17/50

CPC分类号： G06F11/261

摘要： A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals.

摘要翻译： 合成器处理电路的寄存器传输级（RTL）网表描述，以产生保留由RTL网表引用的所有信号的非优化门级网表。 然后处理门级网表以识别电路的存储器件，并确定其内部信号（除电路和存储器件输入和输出信号之外的所有信号）及其它信号（电路和存储器件输入和输出信号）之间的逻辑关系， 。 然后，合成器再次处理RTL网表以产生优化的门级网表，其保留所识别的存储器件，但省略了对某些或全部内部信号的引用。 电路验证系统然后处理优化的门级网表以产生表示电路的其他信号的时变行为的波形数据。 然后根据所确定的内部信号与其他信号之间的逻辑关系，处理波形数据以产生表示由RTL网表参考的内部信号的行为的附加波形数据。

公开(公告)号：US20080250378A1

公开(公告)日：2008-10-09

申请号：US11697869

申请日：2007-04-09

申请人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

发明人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

IPC分类号： H03K17/693

CPC分类号： G06F11/261

摘要： A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals.

摘要翻译： 合成器处理电路的寄存器传输级（RTL）网表描述，以产生保留由RTL网表引用的所有信号的非优化门级网表。 然后处理门级网表以识别电路的存储器件，并确定其内部信号（除电路和存储器件输入和输出信号之外的所有信号）及其它信号（电路和存储器件输入和输出信号）之间的逻辑关系， 。 然后，合成器再次处理RTL网表以产生优化的门级网表，其保留所识别的存储器件，但省略了对某些或全部内部信号的引用。 电路验证系统然后处理优化的门级网表以产生表示电路的其他信号的时变行为的波形数据。 然后根据所确定的内部信号与其他信号之间的逻辑关系，处理波形数据以产生表示由RTL网表参考的内部信号的行为的附加波形数据。

公开(公告)号：US07366652B2

公开(公告)日：2008-04-29

申请号：US11230999

申请日：2005-09-19

申请人： Ming Yang Wang ,  Duan-Ping Chen ,  Swey Yan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui

发明人： Ming Yang Wang ,  Duan-Ping Chen ,  Swey Yan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui

IPC分类号： G06F9/44 ,  G06F13/00

CPC分类号： G06F17/5027

摘要： A co-verification system includes a computer programmed to act as a simulator for simulating behavior of a first portion of an electronic device under test (DUT) by acquiring, processing and generating data representing DUT signals. The co-verification system also includes emulation resources programmed to emulate a second portion of the DUT by receiving, processing and generating emulation signals representing DUT signals. The signals of the DUT are mapped to separate addresses within a memory space, and the simulator controls and reads states of emulation signals by writing data to and reading data from addresses of the memory space states mapped to the DUT signals the emulation signals represent. The computer and the emulation resources are also programmed to implement transactors communicating with one another through a packet routing network. The transactors set states of the emulation signals when the simulator writes to memory space addresses and for reading states of the emulation signals. The transactors monitor states of emulation signals and return data indicating those states to the simulator when the simulator reads memory space addresses mapped to DUT signals represented by the emulation signals.

摘要翻译： 共同验证系统包括被编程为通过获取，处理和产生表示DUT信号的数据来充当用于模拟被测电子设备（DUT）的第一部分的行为的模拟器的计算机。 共同验证系统还包括被编程为通过接收，处理和产生表示DUT信号的仿真信号来模拟DUT的第二部分的仿真资源。 DUT的信号被映射到存储器空间内的分离的地址，并且仿真器通过向映射到仿真信号表示的DUT信号的存储器空间状态的地址写入数据并从其读取数据来控制和读取仿真信号的状态。 计算机和仿真资源也被编程为通过分组路由网络实现彼此通信的交易者。 当模拟器写入存储器空间地址和读取仿真信号的状态时，事务器设置仿真信号的状态。 当模拟器读取映射到由仿真信号表示的DUT信号的存储器空间地址时，事务处理器监视仿真信号的状态并将指示这些状态的数据返回给模拟器。

公开(公告)号：US07120571B2

公开(公告)日：2006-10-10

申请号：US10735342

申请日：2003-12-11

申请人： Sweyyan Shei ,  Ming Yang Wang ,  Vincent Chiu ,  Neu Choo Ngui

发明人： Sweyyan Shei ,  Ming Yang Wang ,  Vincent Chiu ,  Neu Choo Ngui

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/261

摘要： A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.

摘要翻译： 用于电路仿真器的资源板保存可编程逻辑器件（PLD）和诸如随机存取存储器（RAM）的其他仿真资源，并且采用硬连线和基于网络的虚拟信号路径来在资源上的仿真资源之间灵活地路由信号 董事会和资源安置在其他资源板，工作站和其他外部设备上。 资源板还提供将时钟信号传送到PLD所需的逻辑和平衡信号路径，并通过实现测试仿真电路所需的大量模式生成和数据采集功能，减少与外部测试设备通信所需的信号数量。

公开(公告)号：US20130035925A1

公开(公告)日：2013-02-07

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F9/455

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。

公开(公告)号：US08732650B2

公开(公告)日：2014-05-20

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。

公开(公告)号：US07117143B2

公开(公告)日：2006-10-03

申请号：US10735341

申请日：2003-12-11

申请人： Ming Yang Wang ,  Sweyyan Shei ,  Vincent Chiu

发明人： Ming Yang Wang ,  Sweyyan Shei ,  Vincent Chiu

IPC分类号： G06F9/455

CPC分类号： G06F17/5027

摘要： Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including clocked devices (“clock sinks”) such a flip-flops, registers and latches for synchronizing communication between blocks of logic within the IC. The tool initially classifies the clock signal input to each clock sink according to its clock domain, sub-domain and phase. The tool then classifies each synchronizing circuit according to relationships between the classifications of the clock signals it employs to clock its input and output clock sinks. The tool then determines, based on the classification of each synchronizing circuit, whether the emulator can reliably emulate that synchronizing circuit, or whether the tool should automatically modify the netlist description of the synchronizing circuit so that the emulator can emulate it. The tool also generates a warning when an emulator may not reliably emulate a synchronizing circuit and the tool cannot automatically modify it so that the emulator can reliably emulate it.

摘要翻译： 在使用集成电路的网表描述作为编程电路仿真器的基础之前，时钟分析工具分析网表以识别包括时钟设备（“时钟接收器”）的同步电路，例如用于同步通信的触发器，寄存器和锁存器 在IC内的逻辑块之间。 该工具根据其时钟域，子域和相位，首先将时钟信号输入分配给每个时钟接收器。 然后，该工具根据其采用的时钟信号的分类之间的关系来对每个同步电路进行分类，以对其输入和输出时钟汇点进行时钟。 然后，该工具基于每个同步电路的分类来确定仿真器是否可以可靠地模拟该同步电路，或者该工具是否应该自动修改同步电路的网表描述，使得仿真器可以对其进行仿真。 当仿真器可能无法可靠地仿真同步电路时，此工具也会产生警告，并且该工具无法自动修改它，以便仿真器可以可靠地对其进行仿真。

公开(公告)号：US07072825B2

公开(公告)日：2006-07-04

申请号：US10463057

申请日：2003-06-16

申请人： Ming Yang Wang ,  Sweyyan Shei ,  Vincent Chiu

发明人： Ming Yang Wang ,  Sweyyan Shei ,  Vincent Chiu

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06F11/261

摘要： An apparatus for emulating the behavior of an electronic device under test (DUT) includes a computer and one or more resource boards containing emulation resources suitable for emulating portions of the DUT. Each resource board includes transaction device for communicating with one another and with the computer network via data packets transmitted over a packet routing network. The packet routing network and the transaction device on each resource board provide “virtual signal paths” between input and output terminals of resources mounted on separate resource boards. To do so, a transaction device on one resource board sends packets containing data indicating output signal states of local emulation resources to a transaction device on another resource board when then drives signals supplied to input terminals of its local emulation resources to the states indicated by the data conveyed in the packet. When the workstation is to emulate a portion of the DUT, the packet routing network also provides virtual signal paths between the workstation and the resource boards. The computer also transmits programming data to the emulation resources via the packet routing network.

摘要翻译： 用于模拟被测电子设备（DUT）的行为的装置包括计算机和包含适于仿真DUT的部分的仿真资源的一个或多个资源板。 每个资源板包括用于通过数据包路由网络传输的数据分组彼此通信和与计算机网络通信的交易设备。 每个资源板上的分组路由网络和交易设备在安装在单独的资源板上的资源的输入和输出终端之间提供“虚拟信号路径”。 为此，当一个资源板上的事务处理装置将包含指示本地仿真资源的输出信号状态的数据的数据包发送到另一个资源板上的一个交易设备，然后将提供给其本地仿真资源的输入端的信号驱动到由 在数据包中传送的数据。 当工作站模拟DUT的一部分时，分组路由网络还在工作站和资源板之间提供虚拟信号路径。 计算机还经由分组路由网络将编程数据发送到仿真资源。

公开(公告)号：US20120082574A1

公开(公告)日：2012-04-05

申请号：US12894178

申请日：2010-09-30

申请人： Ming Yang Wang

发明人： Ming Yang Wang

IPC分类号： F04B45/00

CPC分类号： F04B43/04 ,  F04B17/042 ,  F04B45/027

摘要： An electromagnetic pump has a frequency converter circuit for driving the electromagnetic pump, wherein the frequency converter circuit comprises an oscillator circuit, a bistable circuit and a push-pull circuit. The oscillator circuit oscillates to transform DC into a single-phase oscillating signal. The bistable circuit splits the single-phase oscillating signal into a N-phase stimulus signal and a S-phase stimulus signal. The push-pull circuit amplifies and transports the N-phase stimulus signal and the S-phase stimulus signal to the electromagnetic pump to make the swing arms of the electromagnetic pump swinging effectively, wherein the swing speed, the swing frequency and the swing amplitude of the swing arms vary with the change of the oscillation frequency of the oscillator circuit. Thereby, the suction pressure and the discharge pressure of the electromagnetic pump could further be adjusted higher or lower, wherein said frequency converter circuit comprises a modulation circuit, which could change the swing speed of the swing arms swinging outwardly or inwardly to further increase or decrease the suction pressure or the discharge pressure.

摘要翻译： 电磁泵具有用于驱动电磁泵的变频器电路，其中变频器电路包括振荡电路，双稳态电路和推挽电路。 振荡器电路振荡以将DC变换为单相振荡信号。 双稳态电路将单相振荡信号分为N相激励信号和S相激励信号。 推挽电路将N相激励信号和S相刺激信号放大并传输到电磁泵，使电磁泵的摆臂有效摆动，其中摆动速度，摆动频率和摆幅振幅 摆臂随着振荡电路的振荡频率的变化而变化。 因此，电磁泵的吸入压力和排出压力可以进一步被调节为更高或更低，其中所述变频器电路包括调制电路，其可以改变摆臂向外或向内摆动以进一步增加或减少的摆动速度 吸入压力或排出压力。

公开(公告)号：US20090010778A1

公开(公告)日：2009-01-08

申请号：US12231218

申请日：2008-08-29

申请人： Ming Yang Wang

发明人： Ming Yang Wang

IPC分类号： F04B43/04 ,  F04B43/073

CPC分类号： F04B43/026 ,  F04B43/04 ,  F04B43/084 ,  F04B45/022 ,  F04B45/027

摘要： A diaphragm pumping device includes a housing having a partition to form an upper chamber and a lower chamber, an inlet port for receiving a fluid, and an outlet port, a bladder attached to the housing and having a compartment communicating with the chambers of the housing, two check valves disposed between the bladder and the chambers of the housing, and an electro-magnetic device actuates the arm to depress and to expand the bladder in order to draw the fluid form the inlet port of the housing toward the outlet port of the housing, the outlet port is communicating with the lower chamber of the housing for allowing the fluid to be completely pumped out of the lower chamber of the housing.

摘要翻译： 膜片泵送装置包括具有分隔壁以形成上室和下室的壳体，用于接收流体的入口端口和出口端口，附接到壳体的气囊，并具有与壳体的腔室连通的隔室 设置在气囊和壳体的室之间的两个止回阀，并且电磁装置致动臂以压缩和膨胀气囊，以便将流体从壳体的入口端口朝向壳体的出口端口 出口端口与壳体的下腔室连通，以允许流体被完全泵出壳体的下腔室。