公开(公告)号：US20130035925A1

公开(公告)日：2013-02-07

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F9/455

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。

公开(公告)号：US07970597B2

公开(公告)日：2011-06-28

申请号：US12120895

申请日：2008-05-15

申请人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

发明人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

IPC分类号： G06F9/455

CPC分类号： G06F17/5027 ,  G06F11/261

摘要： A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect.

摘要翻译： 电路仿真器包括被编程为仿真电路的仿真资源，用于由仿真资源实现的时钟逻辑的时钟系统，资源接口电路，逻辑分析器和调试器。 资源接口电路向仿真资源提供输入信号，存储表示响应于输入信号产生的仿真资源产生的信号的行为的数据，并配置计时系统的操作特性。 在检测到所选择的仿真资源信号中的指定事件时，逻辑分析器断言触发信号，告诉时钟系统停止对仿真资源的计时。 通过分组路由网络与资源接口电路和逻辑分析仪进行通信，调试器获取并处理资源接口电路存储的数据，并向资源接口电路和逻辑分析仪发送命令，指定时钟系统的运行特性，控制信号数据 传输到调试器，并定义逻辑分析仪要检测的信号事件。

公开(公告)号：US20050131670A1

公开(公告)日：2005-06-16

申请号：US10735341

申请日：2003-12-11

申请人： Ming Wang ,  Sweyyan Shei ,  Vincent Chiu

发明人： Ming Wang ,  Sweyyan Shei ,  Vincent Chiu

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027

摘要： Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including clocked devices (“clock sinks”) such a flip-flops, registers and latches for synchronizing communication between blocks of logic within the IC. The tool initially classifies the clock signal input to each clock sink according to its clock domain, sub-domain and phase. The tool then classifies each synchronizing circuit according to relationships between the classifications of the clock signals it employs to clock its input and output clock sinks. The tool then determines, based on the classification of each synchronizing circuit, whether the emulator can reliably emulate that synchronizing circuit, or whether the tool should automatically modify the netlist description of the synchronizing circuit so that the emulator can emulate it. The tool also generates a warning when an emulator may not reliably emulate a synchronizing circuit and the tool cannot automatically modify it so that the emulator can reliably emulate it.

摘要翻译： 在使用集成电路的网表描述作为编程电路仿真器的基础之前，时钟分析工具分析网表以识别包括时钟设备（“时钟接收器”）的同步电路，例如用于同步通信的触发器，寄存器和锁存器 在IC内的逻辑块之间。 该工具根据其时钟域，子域和相位，首先将时钟信号输入分配到每个时钟信宿。 然后，该工具根据其采用的时钟信号的分类之间的关系来对每个同步电路进行分类，以对其输入和输出时钟汇点进行时钟。 然后，该工具基于每个同步电路的分类来确定仿真器是否可以可靠地模拟该同步电路，或者该工具是否应该自动修改同步电路的网表描述，使得仿真器可以对其进行仿真。 当仿真器可能无法可靠地仿真同步电路时，此工具也会产生警告，并且该工具无法自动修改它，以便仿真器可以可靠地对其进行仿真。

公开(公告)号：US08732650B2

公开(公告)日：2014-05-20

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。

公开(公告)号：US20090287468A1

公开(公告)日：2009-11-19

申请号：US12120895

申请日：2008-05-15

申请人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

发明人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

IPC分类号： G06F9/455

CPC分类号： G06F17/5027 ,  G06F11/261

摘要： A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect.

摘要翻译： 电路仿真器包括被编程为仿真电路的仿真资源，用于由仿真资源实现的时钟逻辑的时钟系统，资源接口电路，逻辑分析器和调试器。 资源接口电路向仿真资源提供输入信号，存储表示响应于输入信号产生的仿真资源产生的信号的行为的数据，并配置计时系统的操作特性。 在检测到所选择的仿真资源信号中的指定事件时，逻辑分析器断言触发信号，告诉时钟系统停止对仿真资源的计时。 通过分组路由网络与资源接口电路和逻辑分析仪进行通信，调试器获取并处理资源接口电路存储的数据，并向资源接口电路和逻辑分析仪发送命令，指定时钟系统的运行特性，控制信号数据 传输到调试器，并定义逻辑分析仪要检测的信号事件。

公开(公告)号：US20130055177A1

公开(公告)日：2013-02-28

申请号：US13596069

申请日：2012-08-28

申请人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

发明人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/14

摘要： User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

摘要翻译： 对用户的RTL设计进行分析和检测，以便保留感兴趣的信号，并在合成后将其置于网络列表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网络列表中，以确保在运行时可以访问信号值。 之后，执行P＆R处理，并分析输出以将信号名称与FPGA中的寄存器（触发器和锁存器）或存储器块位置相关联。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US07703054B2

公开(公告)日：2010-04-20

申请号：US11697869

申请日：2007-04-09

申请人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

发明人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

IPC分类号： G06F17/50

CPC分类号： G06F11/261

摘要： A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals.

摘要翻译： 合成器处理电路的寄存器传输级（RTL）网表描述，以产生保留由RTL网表引用的所有信号的非优化门级网表。 然后处理门级网表以识别电路的存储器件，并确定其内部信号（除电路和存储器件输入和输出信号之外的所有信号）及其它信号（电路和存储器件输入和输出信号）之间的逻辑关系， 。 然后，合成器再次处理RTL网表以产生优化的门级网表，其保留所识别的存储器件，但省略了对某些或全部内部信号的引用。 电路验证系统然后处理优化的门级网表以产生表示电路的其他信号的时变行为的波形数据。 然后根据所确定的内部信号与其他信号之间的逻辑关系，处理波形数据以产生表示由RTL网表参考的内部信号的行为的附加波形数据。

公开(公告)号：US20080250378A1

公开(公告)日：2008-10-09

申请号：US11697869

申请日：2007-04-09

申请人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

发明人： Duan-Ping Chen ,  Sweyyan Shei ,  Hung Chun Chiu ,  Neu Choo Ngui ,  Ming Yang Wang

IPC分类号： H03K17/693

CPC分类号： G06F11/261

摘要： A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals.

摘要翻译： 合成器处理电路的寄存器传输级（RTL）网表描述，以产生保留由RTL网表引用的所有信号的非优化门级网表。 然后处理门级网表以识别电路的存储器件，并确定其内部信号（除电路和存储器件输入和输出信号之外的所有信号）及其它信号（电路和存储器件输入和输出信号）之间的逻辑关系， 。 然后，合成器再次处理RTL网表以产生优化的门级网表，其保留所识别的存储器件，但省略了对某些或全部内部信号的引用。 电路验证系统然后处理优化的门级网表以产生表示电路的其他信号的时变行为的波形数据。 然后根据所确定的内部信号与其他信号之间的逻辑关系，处理波形数据以产生表示由RTL网表参考的内部信号的行为的附加波形数据。

公开(公告)号：US07120571B2

公开(公告)日：2006-10-10

申请号：US10735342

申请日：2003-12-11

申请人： Sweyyan Shei ,  Ming Yang Wang ,  Vincent Chiu ,  Neu Choo Ngui

发明人： Sweyyan Shei ,  Ming Yang Wang ,  Vincent Chiu ,  Neu Choo Ngui

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/261

摘要： A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.

摘要翻译： 用于电路仿真器的资源板保存可编程逻辑器件（PLD）和诸如随机存取存储器（RAM）的其他仿真资源，并且采用硬连线和基于网络的虚拟信号路径来在资源上的仿真资源之间灵活地路由信号 董事会和资源安置在其他资源板，工作站和其他外部设备上。 资源板还提供将时钟信号传送到PLD所需的逻辑和平衡信号路径，并通过实现测试仿真电路所需的大量模式生成和数据采集功能，减少与外部测试设备通信所需的信号数量。

公开(公告)号：US08739089B2

公开(公告)日：2014-05-27

申请号：US13596069

申请日：2012-08-28

申请人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

发明人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F7/62

CPC分类号： G06F17/5054 ,  G06F2217/14

摘要： User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

摘要翻译： 用户的寄存器传输级别（RTL）设计进行分析和检测，以使感兴趣的信号得以保留，并且可以在合成后位于网表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网表中，以确保在运行时可以访问信号值。 之后，执行位置和路由（P＆R）处理，并分析输出以将信号名称与现场可编程门阵列（FPGA）器件中的寄存器（触发器和锁存器）或存储器块位置相关联。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。