公开(公告)号：US5497355A

公开(公告)日：1996-03-05

申请号：US253842

申请日：1994-06-03

申请人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

发明人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

IPC分类号： G06F12/06 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18 ,  G06F12/0607 ,  G06F2212/2022

摘要： Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has first and second master latches to receive and store an external address. A first slave latch is also included to receive and store the external address from the first master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the second master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.

摘要翻译： 描述了具有至少第一和第二组存储器阵列的存储器件的同步地址锁存电路。 锁存电路具有用于接收和存储外部地址的第一和第二主锁存器。 如果外部地址属于第一个存储区并且将外部地址作为第一个地址提供给第一个存储体，则还包括一个第一从锁存器，用于从第一主锁存器接收和存储外部地址。 如果外部地址属于第二组，并且将外部地址作为第二地址提供给第二组，则包括第二从锁存器以从第二主锁存器接收和存储外部地址。

公开(公告)号：US5586081A

公开(公告)日：1996-12-17

申请号：US447629

申请日：1995-05-23

申请人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

发明人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

IPC分类号： G06F12/06 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18 ,  G06F12/0607 ,  G06F2212/2022

摘要： Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.

摘要翻译： 描述了具有至少第一和第二组存储器阵列的存储器件的同步地址锁存电路。 锁存电路具有用于接收和存储外部地址的主锁存器。 如果外部地址属于第一个存储区，并且将外部地址作为第一个地址提供给第一个存储区，还包括一个第一从锁存器，用于从主存储器接收和存储外部地址。 如果外部地址属于第二组，则包括第二从锁存器以接收并存储来自主锁存器的外部地址，并将外部地址作为第二地址提供给第二存储体。