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    Synchronous address latching for memory arrays
    1.
    发明授权
    Synchronous address latching for memory arrays 失效
    存储器阵列的同步地址锁存

    公开(公告)号：US5497355A

    公开(公告)日：1996-03-05

    申请号：US253842

    申请日：1994-06-03

    申请人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

    发明人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

    IPC分类号： G06F12/06 ,  G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G06F12/0607 ,  G06F2212/2022

    摘要： Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has first and second master latches to receive and store an external address. A first slave latch is also included to receive and store the external address from the first master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the second master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.

    摘要翻译： 描述了具有至少第一和第二组存储器阵列的存储器件的同步地址锁存电路。 锁存电路具有用于接收和存储外部地址的第一和第二主锁存器。 如果外部地址属于第一个存储区并且将外部地址作为第一个地址提供给第一个存储体，则还包括一个第一从锁存器，用于从第一主锁存器接收和存储外部地址。 如果外部地址属于第二组，并且将外部地址作为第二地址提供给第二组，则包括第二从锁存器以从第二主锁存器接收和存储外部地址。

    Synchronous address latching for memory arrays
    2.
    发明授权
    Synchronous address latching for memory arrays 失效
    存储器阵列的同步地址锁存

    公开(公告)号：US5586081A

    公开(公告)日：1996-12-17

    申请号：US447629

    申请日：1995-05-23

    申请人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

    发明人： Duane R. Mills ,  Richard Fackenthal ,  Rod Rozman ,  Mamun Rashid

    IPC分类号： G06F12/06 ,  G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G06F12/0607 ,  G06F2212/2022

    摘要： Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.

    摘要翻译： 描述了具有至少第一和第二组存储器阵列的存储器件的同步地址锁存电路。 锁存电路具有用于接收和存储外部地址的主锁存器。 如果外部地址属于第一个存储区，并且将外部地址作为第一个地址提供给第一个存储区，还包括一个第一从锁存器，用于从主存储器接收和存储外部地址。 如果外部地址属于第二组，则包括第二从锁存器以接收并存储来自主锁存器的外部地址，并将外部地址作为第二地址提供给第二存储体。

    Flash memory including a mode register for indicating synchronous or asynchronous mode of operation
    5.
    发明授权
    Flash memory including a mode register for indicating synchronous or asynchronous mode of operation 失效
    闪存包括用于指示同步或异步操作模式的模式寄存器

    公开(公告)号：US6026465A

    公开(公告)日：2000-02-15

    申请号：US897499

    申请日：1997-06-18

    申请人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

    发明人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

    IPC分类号： G06F12/06 ,  G06F12/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

    CPC分类号： G06F12/08 ,  G06F12/0607 ,  G11C7/1045 ,  G11C7/1072 ,  G06F2212/2022 ,  Y02B60/1225

    摘要： A flash memory chip that can be switched into four different read modes is described. In the first read mode, asynchronous flash mode, the flash memory is read as a standard flash memory where the reading of the contents of a first address must be completed before a second address to be read can be specified. In the second read mode, synchronous flash mode, a clock signal is provided to the flash chip and a series of addresses belonging to a data burst are specified, one address per clock tick. Then, the contents stored at the addresses specified for the burst are output sequentially during subsequent clock ticks in the order in which the addresses were provided. Alternately, if a single address is provided to the flash chip when it is in the synchronous mode, the subsequent addresses for the burst will be generated within the flash chip and the data burst will then be provided as output from the flash chip. In the third read mode, asynchronous DRAM mode, the row and column addresses are strobed into the flash memory using strobe signals. The flash memory then converts the row and column addresses internally into a single address and provides as output the data stored at that single address. The flash memory does not need an extended precharge period or to be refreshed, but can be controlled by a standard DRAM controller. In the fourth read mode, synchronous DRAM mode, the flash memory emulates a synchronous DRAM.

    摘要翻译： 描述可以切换成四种不同读取模式的闪存芯片。 在第一读取模式，异步闪存模式下，闪存被读取为标准闪速存储器，其中在可以指定要读取的第二地址之前必须先完成读取第一地址的内容。 在第二读取模式的同步闪光模式中，向闪存芯片提供时钟信号，并且指定属于数据突发的一系列地址，每个时钟刻度一个地址。 然后，按照提供地址的顺序，在随后的时钟周期期间顺序输出存储在针对脉冲串指定的地址的内容。 或者，如果在闪存芯片处于同步模式时提供单个地址，则在闪存芯片内将生成用于突发的后续地址，然后将数据突发作为闪存芯片的输出提供。 在第三读取模式下，异步DRAM模式，使用选通信号将行和列地址选通闪存。 然后，闪存将内部的行和列地址转换为单个地址，并提供存储在该单个地址的数据的输出。 闪存不需要扩展预充电周期或刷新，而是可以由标准DRAM控制器控制。 在第四读取模式，同步DRAM模式下，闪速存储器模拟同步DRAM。

    Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
    6.
    发明授权
    Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory 失效
    用于在异步非易失性存储器中执行突发读取操作的方法和装置

    公开(公告)号：US5696917A

    公开(公告)日：1997-12-09

    申请号：US253499

    申请日：1994-06-03

    申请人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

    发明人： Duane R. Mills ,  Brian Lyn Dipert ,  Sachidanandan Sambandan ,  Bruce McCormick ,  Richard D. Pashley

    IPC分类号： G06F12/06 ,  G06F12/08 ,  G11C7/10 ,  G06F12/00

    CPC分类号： G06F12/08 ,  G06F12/0607 ,  G11C7/1045 ,  G11C7/1072 ,  G06F2212/2022 ,  Y02B60/1225

    摘要： An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page. The process of providing consecutive subsequent addresses and enabling the output of a memory component identified by the n lower order bits is repeated as long as the current and preceding addresses identify the same page.

    摘要翻译： 异步非易失性存储器包括多个单独的存储器组件。 突发读取操作参考以第一地址开头的连续地址，其中连续地址不位于相同的存储器组件中。 在异步非易失性存储器中执行突发读取操作的方法包括将第一地址作为当前地址提供给多个单独的组件的步骤。 选择当前地址的m个更高阶位所标识的当前页。 每个单独的存储器组件感测由m个更高阶位确定的位置。 根据当前地址的n个较低位使能所选择的各个存储器组件的输出。 提供连续的后续地址，其中当前地址变为前一地址，并且连续的后续地址变为当前地址。 如果当前地址和以前的地址标识同一页，则由当前地址的n个较低位确定的另一个选定的单独存储器组件的输出被启用而不产生等待状态。 只要当前和前面的地址标识相同的页面，就重复提供连续的后续地址并且使得能够输出由n个较低位比特识别的存储器组件的处理。

    Method and circuitry for preventing propagation of undesired ATD pulses in a flash memory device
    7.
    发明授权
    Method and circuitry for preventing propagation of undesired ATD pulses in a flash memory device 失效
    用于防止闪速存储器件中不需要的ATD脉冲传播的方法和电路

    公开(公告)号：US5563843A

    公开(公告)日：1996-10-08

    申请号：US401474

    申请日：1995-03-09

    申请人： Richard E. Fackenthal ,  Duane R. Mills

    发明人： Richard E. Fackenthal ,  Duane R. Mills

    IPC分类号： G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/18

    摘要： An Address Transition Detection (ATD) circuit for use in memory devices. The ATD circuit includes a pulse generator for generating an ATD pulse. For asynchronous memory device, the pulse generator generates the ATD pulse in response to an address transition, wherein for synchronous devices, the pulse generator generates the ATD pulse in response to control signals that indicate a valid address. The ATD circuit also includes a control circuit and a mask circuit. The control circuit is operative to asserting a first control signal in response to receiving the pulse. The mask circuit is coupled between the output of the pulse generator and the control circuit for preventing propagation of the ATD pulse if the first control signal is active.

    摘要翻译： 用于存储器件的地址转换检测（ATD）电路。 ATD电路包括用于产生ATD脉冲的脉冲发生器。 对于异步存储器件，脉冲发生器响应于地址转换产生ATD脉冲，其中对于同步器件，脉冲发生器响应于指示有效地址的控制信号产生ATD脉冲。 ATD电路还包括控制电路和掩模电路。 响应于接收脉冲，控制电路用于确定第一控制信号。 如果第一控制信号有效，则掩模电路耦合在脉冲发生器的输出端和控制电路之间，以防止ATD脉冲传播。

    Nonvolatile memory with a programmable output of selectable width and a method for controlling the nonvolatile memory to switch between different output widths
    8.
    发明授权
    Nonvolatile memory with a programmable output of selectable width and a method for controlling the nonvolatile memory to switch between different output widths 失效
    具有可选择宽度的可编程输出的非易失性存储器和用于控制非易失性存储器在不同输出宽度之间切换的方法

    公开(公告)号：US5504875A

    公开(公告)日：1996-04-02

    申请号：US32686

    申请日：1993-03-17

    申请人： Duane R. Mills ,  Peter K. Hazen

    发明人： Duane R. Mills ,  Peter K. Hazen

    IPC分类号： G06F12/04 ,  G11C5/00 ,  G11C7/10 ,  G06F12/00

    CPC分类号： G11C7/1006 ,  G06F12/04

    摘要： A nonvolatile memory and a method for controlling the nonvolatile memory to switch between first and second data widths are described. The nonvolatile memory includes a first memory array, a second memory array, a first plurality of data pads, and a second plurality of data pads. A data width control circuit selectively couples the first and second plurality of data pads to the first and second memory arrays. A data width configuration cell is provided for configuring data width of the nonvolatile memory. A data width select circuit controls the data width control circuit to selectively couple the first and second plurality of data pads to the first and second memory arrays under the control of the data width configuration cell. When the data width configuration cell is in a first state, the first and second memory arrays are coupled to the first and second plurality of data pads such that the nonvolatile memory has a first data width. When the data width configuration cell is in a second state, the first and second memory arrays are coupled to the first plurality of data pads such that the nonvolatile memory has a second data width.

    摘要翻译： 描述了非易失性存储器和用于控制非易失性存储器以在第一和第二数据宽度之间切换的方法。 非易失性存储器包括第一存储器阵列，第二存储器阵列，第一多个数据焊盘和第二多个数据焊盘。 数据宽度控制电路选择性地将第一和第二多个数据焊盘耦合到第一和第二存储器阵列。 提供了用于配置非易失性存储器的数据宽度的数据宽度配置单元。 数据宽度选择电路控制数据宽度控制电路，以在数据宽度配置单元的控制下选择性地将第一和第二多个数据焊盘耦合到第一和第二存储器阵列。 当数据宽度配置单元处于第一状态时，第一和第二存储器阵列耦合到第一和第二多个数据焊盘，使得非易失性存储器具有第一数据宽度。 当数据宽度配置单元处于第二状态时，第一和第二存储器阵列耦合到第一多个数据焊盘，使得非易失性存储器具有第二数据宽度。

    Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets
    10.
    发明授权
    Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets 失效
    非易失性存储器，具有阻塞的冗余列和相应的内容可寻址存储器集

    公开(公告)号：US5347484A

    公开(公告)日：1994-09-13

    申请号：US216766

    申请日：1994-03-23

    申请人： Phillip M. Kwong ,  Sachidanandan Sambandan ,  Sherif R. B. Sweha ,  Duane R. Mills

    发明人： Phillip M. Kwong ,  Sachidanandan Sambandan ,  Sherif R. B. Sweha ,  Duane R. Mills

    IPC分类号： G11C29/00 ,  G11C11/40

    CPC分类号： G11C29/808

    摘要： A nonvolatile memory device is described. The memory device includes a main memory array for storing data. The main memory array comprises a first block and a second block. A redundant memory array comprises a first redundant block and a second redundant block. The first redundant block comprises a first redundant column of memory cells and a second redundant column of memory cells. The second redundant block comprises a third redundant column of memory cells and a fourth redundant column of memory cells. A content addressable memory (CAM) comprises a first set of CAM cells for storing a first address of a first defective column in the main memory array and a second set of CAM cells for storing a second address of a second defective column in the main memory array. The first set of CAM cells cause the first redundant column in the first redundant block to replace the first defective column when the first defective column is in the first block. The first set of CAM cells cause the third redundant column in the second redundant block to replace the first defective column when the first defective column is in the second block. The second set of CAM cells cause the second redundant column in the first redundant block to replace the second defective column when the second defective column is in the first block. The second set of CAM cells cause the fourth redundant column in the second redundant block to replace the second defective column when the second defective column is in the second block.

    摘要翻译： 描述非易失性存储器件。 存储器件包括用于存储数据的主存储器阵列。 主存储器阵列包括第一块和第二块。 冗余存储器阵列包括第一冗余块和第二冗余块。 第一冗余块包括存储器单元的第一冗余列和存储器单元的第二冗余列。 第二冗余块包括存储器单元的第三冗余列和存储器单元的第四冗余列。 内容可寻址存储器（CAM）包括用于存储主存储器阵列中的第一缺陷列的第一地址的第一组CAM单元和用于存储主存储器中的第二缺陷列的第二地址的第二组CAM单元 数组。 当第一个缺陷列在第一个块中时，第一组CAM单元使第一个冗余块中的第一个冗余列替换第一个缺陷列。 当第一个缺陷列在第二个块中时，第一组CAM单元使第二个冗余块中的第三个冗余列替换第一个缺陷列。 当第二个缺陷列在第一个块中时，第二组CAM单元使第一个冗余块中的第二个冗余列替换第二个缺陷列。 当第二个缺陷列在第二个块中时，第二组CAM单元使第二个冗余块中的第四个冗余列替换第二个缺陷列。