MAP decoding for turbo codes by parallel matrix processing
    1.
    发明授权
    MAP decoding for turbo codes by parallel matrix processing 失效
    通过并行矩阵处理对turbo码进行MAP解码

    公开(公告)号:US06606725B1

    公开(公告)日:2003-08-12

    申请号:US09558440

    申请日:2000-04-25

    IPC分类号: H03M1345

    摘要: A matrix transform method and circuit provides for MAP decoding of turbo codes. The method begins by initializing a forward recursion probability function vector &agr;0, and a backward recursion probability function vector &bgr;N. Then, transition probability matrices &Ggr;(Rk) and &Ggr;i(Rk) are determined according to each received symbol of the sequence R1N. And then, values of &agr;k, corresponding to the received Rk are determined according to &Ggr;(Rk). At the same time of determining &agr;k, a plurality of multiplacation on &Ggr;(Rk) and &Ggr;i(Rk) are accomplished in parallel. By making use of the results of the matrix multiplications, after receiving the complete symbol sequence R1N, values of all of the backward recursion probability vector &bgr;k, where k=1, 2, . . . , N−1, are determined in parallel, and the log likelihood ratio for every decoded bit dk, k=1, 2, . . . , N, are also determined in parallel. The circuit performs successive decoding procedures in parallel using a set of regular matrix operations. These operations substantially accelerate the decoding speed and reduce the computational complexity, and are particularly suited for implementation in special-purpose parallel processing VLSI hardware architectures. Using shift registers, the VLSI implementation effectively reduces memory requirements and simplifies complicated data accesses and transfers.

    摘要翻译: 矩阵变换方法和电路提供turbo码的MAP解码。 该方法通过初始化前向递归概率函数向量α0和向后递归概率函数向量βN开始。 然后,根据序列R1N的每个接收符号确定转移概率矩阵GAMMA(Rk)和GAMMAi(Rk)。 然后,根据GAMMA(Rk)确定对应于接收到的R k的alphak值。 在确定alphak的同时,GAMMA(Rk)和GAMMAi(Rk)上的多个乘法并行完成。 通过利用矩阵乘法的结果,在接收到完整符号序列R1N之后,所有向后递归概率向量betak的值,其中k = 1,2。 。 。 ,N-1,并且每个解码比特dk的对数似然比k = 1,2。 。 。 ,N也是并行确定的。 该电路使用一组常规矩阵运算来并行地执行连续解码过程。 这些操作大大加快了解码速度并降低了计算复杂度,特别适用于专用并行处理VLSI硬件体系结构中的实现。 使用移位寄存器,VLSI实现有效地减少了内存需求,简化了复杂的数据访问和传输。