公开(公告)号：US07027519B2

公开(公告)日：2006-04-11

申请号：US09796124

申请日：2001-02-28

申请人： Jay Bao ,  Pei Chen ,  Hisashi Kobayashi

发明人： Jay Bao ,  Pei Chen ,  Hisashi Kobayashi

IPC分类号： H04L23/02

CPC分类号： H04L27/2647 ,  H04L25/0236

摘要： In orthogonal frequency division multiplexing systems, iterative maximum likelihood channel estimation and signal detection is preformed. The channel estimation gives the maximum likelihood estimates of time domain channel parameters. A cost function is defined. An iterative process estimates a joint channel impulse response and a transmitted signal that minimize the cost function, and thus solves the channel estimation and signal detection problem jointly without having specific knowledge of the channel.

公开(公告)号：US06650653B1

公开(公告)日：2003-11-18

申请号：US09487095

申请日：2000-01-19

申请人： Jyhchau Horng ,  Jay Bao

发明人： Jyhchau Horng ,  Jay Bao

IPC分类号： H04L2700

CPC分类号： H04B1/0003 ,  H04B1/406 ,  H04B1/707 ,  H04B7/0845 ,  H04B7/2612 ,  H04L25/0228 ,  H04L27/0008

摘要： In a digital radio receiver, transmitted symbols are recovered from a received signal that includes tim-shifted and frequency-shifted copies of a transmitted signal. A channel estimator extracts channel characteristics from a training signal. Receiver data and software for executing in a processor are stored in a memory connected to the processor. A parameter controller generates receiver configuration parameters from the channel characteristics and the receiver data. The received signal is decomposed into a matrix of samples according to the receiver configuration parameters to adapt the receiver to a multiple multiplexing schemes. An inner product is formed of the samples and channel characteristics, and the transmitted symbols are recovered from the inner product.

摘要翻译： 在数字无线电接收机中，从包括发送信号的定时偏移和频移副本的接收信号中恢复发送符号。 信道估计器从训练信号中提取信道特性。 用于在处理器中执行的接收器数据和软件存储在连接到处理器的存储器中。 参数控制器从通道特性和接收器数据生成接收器配置参数。 根据接收机配置参数将接收到的信号分解成采样矩阵，以使接收机适应多重复用方案。 内部产品由样品和通道特性形成，并且从内部产物中回收传输的符号。

公开(公告)号：US06671328B1

公开(公告)日：2003-12-30

申请号：US09287125

申请日：1999-04-07

申请人： Tommy C. Poon ,  Jay Bao ,  Yoshiki Mizutani ,  Hiroyuki Nakayama

发明人： Tommy C. Poon ,  Jay Bao ,  Yoshiki Mizutani ,  Hiroyuki Nakayama

IPC分类号： H04L2720

CPC分类号： H04L27/0008

摘要： A signal having one of a plurality of modulation formats is formed by encoding first data in accordance with a particular one of the modulation formats. The encoded first data is then combined with second data identifying the particular modulation format of the encoded first data to form the signal.

摘要翻译： 通过根据调制格式中的特定一种对第一数据进行编码来形成具有多种调制格式之一的信号。 然后将编码的第一数据与识别编码的第一数据的特定调制格式的第二数据组合以形成信号。

公开(公告)号：US06606725B1

公开(公告)日：2003-08-12

申请号：US09558440

申请日：2000-04-25

申请人： Duanyi Wang ,  Hisashi Kobayashi ,  Jay Bao

发明人： Duanyi Wang ,  Hisashi Kobayashi ,  Jay Bao

IPC分类号： H03M1345

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3933 ,  H03M13/616

摘要： A matrix transform method and circuit provides for MAP decoding of turbo codes. The method begins by initializing a forward recursion probability function vector &agr;0, and a backward recursion probability function vector &bgr;N. Then, transition probability matrices &Ggr;(Rk) and &Ggr;i(Rk) are determined according to each received symbol of the sequence R1N. And then, values of &agr;k, corresponding to the received Rk are determined according to &Ggr;(Rk). At the same time of determining &agr;k, a plurality of multiplacation on &Ggr;(Rk) and &Ggr;i(Rk) are accomplished in parallel. By making use of the results of the matrix multiplications, after receiving the complete symbol sequence R1N, values of all of the backward recursion probability vector &bgr;k, where k=1, 2, . . . , N−1, are determined in parallel, and the log likelihood ratio for every decoded bit dk, k=1, 2, . . . , N, are also determined in parallel. The circuit performs successive decoding procedures in parallel using a set of regular matrix operations. These operations substantially accelerate the decoding speed and reduce the computational complexity, and are particularly suited for implementation in special-purpose parallel processing VLSI hardware architectures. Using shift registers, the VLSI implementation effectively reduces memory requirements and simplifies complicated data accesses and transfers.

摘要翻译： 矩阵变换方法和电路提供turbo码的MAP解码。 该方法通过初始化前向递归概率函数向量α0和向后递归概率函数向量βN开始。 然后，根据序列R1N的每个接收符号确定转移概率矩阵GAMMA（Rk）和GAMMAi（Rk）。 然后，根据GAMMA（Rk）确定对应于接收到的R k的alphak值。 在确定alphak的同时，GAMMA（Rk）和GAMMAi（Rk）上的多个乘法并行完成。 通过利用矩阵乘法的结果，在接收到完整符号序列R1N之后，所有向后递归概率向量betak的值，其中k = 1,2。 。 。 ，N-1，并且每个解码比特dk的对数似然比k = 1,2。 。 。 ，N也是并行确定的。 该电路使用一组常规矩阵运算来并行地执行连续解码过程。 这些操作大大加快了解码速度并降低了计算复杂度，特别适用于专用并行处理VLSI硬件体系结构中的实现。 使用移位寄存器，VLSI实现有效地减少了内存需求，简化了复杂的数据访问和传输。

公开(公告)号：US06192070B1

公开(公告)日：2001-02-20

申请号：US09002438

申请日：1998-01-02

申请人： Tommy C. Poon ,  Jay Bao ,  Yoshiki Mizutani ,  Hiroyuki Nakayama

发明人： Tommy C. Poon ,  Jay Bao ,  Yoshiki Mizutani ,  Hiroyuki Nakayama

IPC分类号： H04B138

CPC分类号： H04B1/005 ,  H04B1/406 ,  H04L1/0003 ,  H04L1/0025 ,  H04L1/0032 ,  H04L27/0008 ,  H04L27/0012 ,  H04L27/2601

摘要： A universal modem has a software-configurable modulator/demodulator which accommodates different modulation formats such as those associated with terrestrial, cable, phone line, satellite and wireless communications to be transmitted and received through a single device in which the modem has reconfigurable logic to accommodate the format of the signals being received or transmitted. In one embodiment, the system tracks channel noise and changes modulation format at both the transmit and receive sides of the system through the use of a controller that controls both sides.

摘要翻译： 通用调制解调器具有软件可配置的调制器/解调器，其适应与地面，电缆，电话线，卫星和无线通信相关联的不同调制格式，以通过单个设备发送和接收，其中调制解调器具有可重构逻辑以容纳 正在接收或发送信号的格式。 在一个实施例中，系统通过使用控制两侧的控制器来跟踪信道噪声并改变系统的发射侧和接收侧的调制格式。

公开(公告)号：US5940438A

公开(公告)日：1999-08-17

申请号：US801748

申请日：1997-02-18

申请人： Tommy C. Poon ,  Jay Bao ,  Yoshiki Mizutani ,  Hiroyuki Nakayama

发明人： Tommy C. Poon ,  Jay Bao ,  Yoshiki Mizutani ,  Hiroyuki Nakayama

IPC分类号： H04N7/10 ,  H04J11/00 ,  H04L27/00 ,  H04L27/18 ,  H04L27/34 ,  H04L29/06 ,  H04B1/38 ,  H01L27/10 ,  H01L27/18 ,  H01L5/16

CPC分类号： H04L27/0008

摘要： A universal modem has a software-configurable modulator/demodulator which commodates different modulation formats such as those associated with terrestrial, cable, phone line, satellite and wireless communications to be transmitted and received through a single device in which the modem has reconfigurable logic to accommodate the format of the signals being received or transmitted. Note that the modulator or demodulator can be used separately or the two units can be combined and used for transceivers, with either the same software configuring both the modulator and demodulator, or with different software used for the two units. In the receive mode, the universal modem detects the modulation format of the incoming signal and reconfigures the logic of its software-configurable demodulator to output demodulated digital data for further processing. In the transmit mode, information to be transmitted is provided with the appropriate modulation format by setting a software-configurable modulator in the universal modem to the particular format. In one embodiment, in the receive mode the incoming signal is A-D converted, with a host processor utilized to detect the type of modulation associated with the incoming signal and through a configuration controller configures a random access memory which is coupled to the software-configurable demodulator. In advanced television applications, the demodulated signal is passed through an equalizer, a Trellis Decoder and Reed-Solomon Decoder to provide an appropriate filtered and level-adjusted digital signal that is coupled to the next processing stage.

摘要翻译： 通用调制解调器具有软件可配置的调制器/解调器，其适应与地面，电缆，电话线，卫星和无线通信相关联的不同调制格式，以通过单个设备发送和接收，其中调制解调器具有可重构逻辑以容纳 正在接收或发送信号的格式。 请注意，调制器或解调器可以单独使用，也可以将两个单元组合使用，用于收发器，同样的软件配置了调制器和解调器，也可以配置两个单元使用不同的软件。 在接收模式下，通用调制解调器检测输入信号的调制格式，并重新配置其软件可配置解调器的逻辑，以输出解调的数字数据进行进一步处理。 在发送模式中，通过将通用调制解调器中的软件可配置调制器设置为特定格式，向被发送的信息提供适当的调制格式。 在一个实施例中，在接收模式中，输入信号被AD转换，主机处理器用于检测与输入信号相关联的调制类型，并且通过配置控制器配置随机存取存储器，该存储器耦合到软件可配置解调器 。 在高级电视应用中，解调的信号通过均衡器，网格解码器和里德 - 索罗门解码器，以提供耦合到下一个处理级的适当的滤波和电平调整的数字信号。

公开(公告)号：US06509934B1

公开(公告)日：2003-01-21

申请号：US09219060

申请日：1998-12-22

申请人： Jay Bao ,  Victor Sinyansky

发明人： Jay Bao ,  Victor Sinyansky

IPC分类号： H04N550

CPC分类号： H01Q1/1257

摘要： An antenna is directed to optimally receive an advanced television signal. First, the strength of the signal is measured as a function of the azimuth angle of the antenna, and second the flatness of the signal is measured as a function of the azimuth angle of the antenna. The antenna is then rotated to maximize the flatness of the signal while maintaining the strength of the signal above a minimum threshold.

摘要翻译： 引导天线以最佳地接收高级电视信号。 首先，测量信号的强度作为天线的方位角的函数，其次测量作为天线的方位角的函数的信号的平坦度。 然后旋转天线以最大化信号的平坦度，同时将信号的强度保持在最小阈值以上。

公开(公告)号：US06449630B1

公开(公告)日：2002-09-10

申请号：US09288097

申请日：1999-04-07

申请人： Jay Bao

发明人： Jay Bao

IPC分类号： G06F1500

CPC分类号： G06F7/5443

摘要： An apparatus for processing digital signals includes a multiplier having a first input and a second input and an output producing a product. An adder is connected to receive the product from the multiplier as a first input to produce a sum. A first register is connected to receive and store the sum and to provide a second input to the adder in response to a clock signal. A second register is connected to receive and store the output of the first register in response to an inverse of the clock signal to enable the addition of two products in a single clock cycle.

摘要翻译： 一种用于处理数字信号的装置包括具有第一输入和第二输入的乘法器以及产生产品的输出。 连接加法器以从乘法器接收产品作为第一输入以产生和。 连接第一寄存器以接收和存储和，并响应于时钟信号向加法器提供第二输入。 连接第二寄存器以响应于时钟信号的反相接收和存储第一寄存器的输出，以使得能够在单个时钟周期内添加两个乘积。

公开(公告)号：US6128357A

公开(公告)日：2000-10-03

申请号：US997772

申请日：1997-12-24

申请人： Cheng-Youn Lu ,  Jay Bao ,  Tommy C. Poon

发明人： Cheng-Youn Lu ,  Jay Bao ,  Tommy C. Poon

IPC分类号： H03H17/06 ,  H04L7/02 ,  H04L7/033 ,  H04L7/00 ,  H03D3/24 ,  H04L25/40 ,  H04L25/36

CPC分类号： H04L7/0029 ,  H04L7/0335

摘要： An adaptable, variable rate symbol timing recovery system for a digital sal receiver comprises an analog to digital (A-D) signal converter having analog signal input and digital data signal output terminals. A source of selectable, substantially fixed rate, data sampling clock signals is coupled to the A-D signal converter for sampling a signal received at the input at a predetermined, substantially fixed clock rate, depending on data rate and modulation of the received signal. A digital signal processing loop is coupled to the digital data signal output terminal for adjustably producing interdependent signals in synchronism with the data signals at the output terminal which are asynchronous with respect to the fixed rate clock signals. A Controller is provided for selectively configuring the data sampling clock signal source and the digital signal processing loop according to the data rate and modulation characteristics of the received signal.

摘要翻译： 用于数字信号接收机的适应性可变速率符号定时恢复系统包括具有模拟信号输入和数字数据信号输出端的模数（A-D）信号转换器。 可选择的基本上固定的速率的数据采样时钟信号的源极耦合到A-D信号转换器，用于根据接收信号的数据速率和调制对预定的基本上固定的时钟速率在输入处接收到的信号进行采样。 数字信号处理环路耦合到数字数据信号输出端子，用于与输出端子上相对于固定速率时钟信号异步的数据信号同步地产生相互依赖的信号。 提供控制器，用于根据接收信号的数据速率和调制特性有选择地配置数据采样时钟信号源和数字信号处理环路。

公开(公告)号：US5835151A

公开(公告)日：1998-11-10

申请号：US648358

申请日：1996-05-15

申请人： Huifang Sun ,  Jay Bao ,  Tommy C. Poon

发明人： Huifang Sun ,  Jay Bao ,  Tommy C. Poon

IPC分类号： H04N7/01 ,  H04N7/26

CPC分类号： H04N7/0125 ,  H04N19/40 ,  H04N19/85

摘要： A method and apparatus for down-converting a digital video signal includes a synthesizer and a converter. The synthesizer receives a digital video signal including at least first and second DCT blocks of DCT coefficients, and synthesizes the first and second DCT blocks into a single synthesized DCT block having dimensions equal to the first and second DCT blocks. The converter converts the synthesized DCT block from the DCT domain to the spatial domain to produce an output digital video signal.

摘要翻译： 用于下变频数字视频信号的方法和装置包括合成器和转换器。 合成器接收包括DCT系数的至少第一和第二DCT块的数字视频信号，并将第一和第二DCT块合成为具有等于第一和第二DCT块的尺寸的单个合成DCT块。 转换器将合成DCT块从DCT域转换为空间域，以产生输出数字视频信号。