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公开(公告)号：US10394988B2
公开(公告)日：2019-08-27
申请号：US15118490
申请日：2014-02-20
IPC分类号： G06F17/50 , H03K19/003 , H03K19/01
摘要： A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ′. The method further comprises providing a commutativity, a majority (Ω.M), an associativity (Ω.A), a distributivity (Ω.D), an inverter propagation (Ω.I), a relevance (Ψ.R), a complementary associativity (Ψ.C), and a substitution (Ψ.S) transformation; and combining the Ω.M, Ω.C, Ω.A, Ω.D, Ω.I, Ψ.R, Ψ.C and Ψ.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the Ω.A, Ω.C, Ω.D, Ω.I, Ψ.R, Ψ.S and Ψ.C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the Ω.M transformation, applied left-to-right, and the Ω.D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iteration of steps (i) and (ii) till a reduction in area is achieved.
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公开(公告)号：US20170177750A1
公开(公告)日：2017-06-22
申请号：US15118490
申请日：2014-02-20
IPC分类号： G06F17/50 , H03K19/01 , H03K19/003
CPC分类号： G06F17/505 , G06F17/50 , G06F17/5068 , G06F17/5081 , G06F2217/08 , G06F2217/16 , G06F2217/78 , G06F2217/84
摘要： A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ′. The method further comprises providing a commutativity, a majority (Ω.M), an associativity (Ω.A), a distributivity (Ω.D), an inverter propagation (Ω.I), a relevance (Ψ.R), a complementary associativity (Ψ.C), and a substitution (Ψ.S) transformation; and combining the Ω.M, Ω.C, Ω.A, Ω.D, Ω.I, Ψ.R, Ψ.C and Ψ.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the Ω.A, Ω.C, Ω.D, Ω.I, Ψ.R, Ψ.S and Ψ.C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the Ω.M transformation, applied left-to-right, and the Ω.D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iteration of steps (i) and (ii) till a reduction in area is achieved.
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