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    Boolean logic optimization in majority-inverter graphs
    1.
    发明授权
    Boolean logic optimization in majority-inverter graphs 有权

    公开(公告)号：US10380309B2

    公开(公告)日：2019-08-13

    申请号：US14727114

    申请日：2015-06-01

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Luca Gaetano Amarù ,  Pierre-Emmanuel Julien Marc Gaillardon ,  Giovanni De Micheli

    IPC分类号： G06F17/50

    摘要： We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent algebraic framework. However, when algebraic methods cannot improve a result quality, stronger Boolean methods are needed to attain further optimization. For this purpose, we propose MIG Boolean methods exploiting the error masking property of majority operators. Our MIG Boolean methods insert logic errors that strongly simplify an MIG while being successively masked by the voting nature of majority nodes. Thanks to the data-structure/methodology fitness, our MIG Boolean methods run in principle as fast as algebraic counterparts. Experiments show that our Boolean methodology combined with state-of-art MIG algebraic techniques enable superior optimization quality. For example, when targeting depth reduction, our MIG optimizer transforms a ripple carry adder into a carry look-ahead one. Considering the set of IWLS'05 (arithmetic intensive) benchmarks, our MIG optimizer reduces by 17.98% (26.69%) the logic network depth while also enhancing size and power activity metrics, with respect to ABC academic optimizer. Without MIG Boolean methods, i.e., using MIG algebraic optimization alone, the previous gains are halved. Employed as front-end to a delay-critical 22-nm ASIC flow (logic synthesis+physical design) our MIG optimizer reduces the average delay/area/power by (15.07%, 4.93%, 1.93%), over 27 academic and industrial benchmarks, as compared to a leading commercial ASIC flow.

    High-performance low-power near-Vt resistive memory-based FPGA
    3.
    发明授权
    High-performance low-power near-Vt resistive memory-based FPGA 有权
    高性能低功率近Vt电阻式存储器FPGA

    公开(公告)号：US09276573B2

    公开(公告)日：2016-03-01

    申请号：US14444422

    申请日：2014-07-28

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Pierre-Emmanuel Gaillardon ,  Xifan Tang ,  Giovanni De Micheli

    IPC分类号： H03K19/177 ,  H03K19/00 ,  H03K19/094

    CPC分类号： H03K19/0013 ,  H03K19/0941 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776

    摘要： A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.

    摘要翻译： 岛型的现场可编程门阵列（FPGA）包括多个基于簇的可配置逻辑块（CLB），由此基于簇的CLB中的每一个由由多个多路复用器形成的全局路由结构包围并通过 组合在开关盒（SB）和连接块（CB）中的传输门），开关盒和连接块包括至少插入在开关盒的第一路由架构的数据路径中的第一多个电阻存储器，以及 连接块。 每个CLB都包含基本逻辑元素（BLE）以及本地路由资源。

    Method for speeding up boolean satisfiability
    5.
    发明授权
    Method for speeding up boolean satisfiability 有权

    公开(公告)号：US09685959B2

    公开(公告)日：2017-06-20

    申请号：US14851131

    申请日：2015-09-11

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Luca Gaetano Amarú ,  Pierre-Emmanuel Julien Marc Gaillardon ,  Giovanni De Micheli

    IPC分类号： G06F9/455 ,  G06F17/50 ,  H03K19/20

    CPC分类号： H03K19/20 ,  G06F17/504 ,  G06N5/006

    摘要： A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic operators; transforming the original circuit obtained from the interpreting, into a dual logic circuit enabled for a checking of contradiction in place of tautology and vice versa, by providing a set of switching rules configured to switch each respective one of the original logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into a respective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN; and complementing outputs of the original circuit by adding an INV at each output wire. The method further provides testing in parallel the satisfiability of the original logic circuit, and the satisfiability of the dual logic circuit with inverted outputs. Responsive to one of the parallel tests finishing, the other parallel test is caused to also stop.

    Majority logic synthesis
    7.
    发明授权
    Majority logic synthesis 有权

    公开(公告)号：US10394988B2

    公开(公告)日：2019-08-27

    申请号：US15118490

    申请日：2014-02-20

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Pierre-Emmanuel Julien Gaillardon ,  Luca Gaetano Amarù ,  Giovanni De Micheli

    IPC分类号： G06F17/50 ,  H03K19/003 ,  H03K19/01

    摘要： A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ′. The method further comprises providing a commutativity, a majority (Ω.M), an associativity (Ω.A), a distributivity (Ω.D), an inverter propagation (Ω.I), a relevance (Ψ.R), a complementary associativity (Ψ.C), and a substitution (Ψ.S) transformation; and combining the Ω.M, Ω.C, Ω.A, Ω.D, Ω.I, Ψ.R, Ψ.C and Ψ.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the Ω.A, Ω.C, Ω.D, Ω.I, Ψ.R, Ψ.S and Ψ.C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the Ω.M transformation, applied left-to-right, and the Ω.D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iteration of steps (i) and (ii) till a reduction in area is achieved.

    Majority Logic Synthesis
    8.
    发明申请
    Majority Logic Synthesis 审中-公开

    公开(公告)号：US20170177750A1

    公开(公告)日：2017-06-22

    申请号：US15118490

    申请日：2014-02-20

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Pierre-Emmanuel Julien Gaillardon ,  Luca Gaetano Amarù ,  Giovanni De Micheli

    IPC分类号： G06F17/50 ,  H03K19/01 ,  H03K19/003

    CPC分类号： G06F17/505 ,  G06F17/50 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/08 ,  G06F2217/16 ,  G06F2217/78 ,  G06F2217/84

    摘要： A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ′. The method further comprises providing a commutativity, a majority (Ω.M), an associativity (Ω.A), a distributivity (Ω.D), an inverter propagation (Ω.I), a relevance (Ψ.R), a complementary associativity (Ψ.C), and a substitution (Ψ.S) transformation; and combining the Ω.M, Ω.C, Ω.A, Ω.D, Ω.I, Ψ.R, Ψ.C and Ψ.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the Ω.A, Ω.C, Ω.D, Ω.I, Ψ.R, Ψ.S and Ψ.C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the Ω.M transformation, applied left-to-right, and the Ω.D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iteration of steps (i) and (ii) till a reduction in area is achieved.

    HIGH-PERFORMANCE LOW-POWER NEAR-VT RESISTIVE MEMORY-BASED FPGA
    9.
    发明申请
    HIGH-PERFORMANCE LOW-POWER NEAR-VT RESISTIVE MEMORY-BASED FPGA 有权
    高性能低功耗近端电阻基于存储器的FPGA

    公开(公告)号：US20160028396A1

    公开(公告)日：2016-01-28

    申请号：US14444422

    申请日：2014-07-28

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Pierre-Emmanuel Gaillardon ,  Xifan Tang ,  Giovanni De Micheli

    IPC分类号： H03K19/00 ,  H03K19/094 ,  H03K19/177

    CPC分类号： H03K19/0013 ,  H03K19/0941 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776

    摘要： A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources.

    摘要翻译： 岛型的现场可编程门阵列（FPGA）包括多个基于簇的可配置逻辑块（CLB），由此基于簇的CLB中的每一个由由多个多路复用器形成的全局路由结构包围并通过 组合在开关盒（SB）和连接块（CB）中的传输门），开关盒和连接块包括至少插入在开关盒的第一路由架构的数据路径中的第一多个电阻存储器，以及 连接块。 每个CLB都包含基本逻辑元素（BLE）以及本地路由资源。