公开(公告)号：US20160373121A1

公开(公告)日：2016-12-22

申请号：US15184113

申请日：2016-06-16

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ja Yol LEE ,  Minjae LEE ,  Cheon Soo KIM ,  Jaehyun KANG ,  Minuk HEO

IPC: H03L7/099 ,  H03L7/093 ,  H03L7/18

CPC classification number: H03L7/093 ,  H03L7/085 ,  H03L7/099 ,  H03L7/18

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.

Abstract translation: 提供了一种产生对应于参考时钟信号的输出时钟信号的锁相环（PLL）。 锁相环（PLL）包括分配器，其被配置为分频输出时钟信号以产生分频时钟信号;时间脉冲转换器，被配置为产生时间脉冲转换信号，该时间脉冲转换信号具有对应于参考的相位差的脉冲 时钟信号和分频时钟信号;以及数字控制振荡器，包括用于产生输出时钟信号的LC谐振电路，并且被配置为控制被确定为对应于LC谐振电路的时间常数的输出时钟信号的频率， 涉及时间脉冲转换信号，其中根据参考时钟信号和分频时钟信号之间的相位差的变化连续地控制改变的电容的维持时间。

公开(公告)号：US20160373115A1

公开(公告)日：2016-12-22

申请号：US15185438

申请日：2016-06-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Ja Yol LEE ,  Minjae LEE ,  Cheon Soo KIM ,  Jaehyun KANG ,  Junsoo KO

IPC: H03L1/00 ,  H03K5/135 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03L7/081 ,  H03L2207/50

Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

Abstract translation: 提供了一种产生对应于参考时钟信号的输出时钟信号的锁相环（PLL），PLL包括第一相位内插器，其被配置为产生具有来自输出时钟信号的第一时间延迟的第一内插时钟信号，以及 第二相位插值器被配置为产生具有来自输出时钟信号的第二时间延迟的第二内插时钟信号。 基于多路复用第一内插时钟信号和第二内插时钟信号，PLL控制输出时钟信号的频率。