-
公开(公告)号：US20160373115A1
公开(公告)日：2016-12-22
申请号：US15185438
申请日：2016-06-17
Inventor： Ja Yol LEE , Minjae LEE , Cheon Soo KIM , Jaehyun KANG , Junsoo KO
CPC classification number: H03K5/135 , H03K2005/00052 , H03L7/081 , H03L2207/50
Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
Abstract translation: 提供了一种产生对应于参考时钟信号的输出时钟信号的锁相环（PLL），PLL包括第一相位内插器，其被配置为产生具有来自输出时钟信号的第一时间延迟的第一内插时钟信号，以及 第二相位插值器被配置为产生具有来自输出时钟信号的第二时间延迟的第二内插时钟信号。 基于多路复用第一内插时钟信号和第二内插时钟信号，PLL控制输出时钟信号的频率。
-
公开(公告)号：US20170257176A1
公开(公告)日：2017-09-07
申请号：US15229950
申请日：2016-08-05
Inventor： Ik Soo EO , Sang-Kyun Kim , Cheon Soo KIM , Jang Hong CHOI
CPC classification number: H04B17/14 , H04B17/0085 , H04B17/104
Abstract: A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.
-
Patent Agency Ranking
公开(公告)号：US20160373121A1
公开(公告)日：2016-12-22
申请号：US15184113
申请日：2016-06-16
Inventor： Ja Yol LEE , Minjae LEE , Cheon Soo KIM , Jaehyun KANG , Minuk HEO
Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.
Abstract translation: 提供了一种产生对应于参考时钟信号的输出时钟信号的锁相环（PLL）。 锁相环（PLL）包括分配器，其被配置为分频输出时钟信号以产生分频时钟信号;时间脉冲转换器，被配置为产生时间脉冲转换信号，该时间脉冲转换信号具有对应于参考的相位差的脉冲 时钟信号和分频时钟信号;以及数字控制振荡器，包括用于产生输出时钟信号的LC谐振电路，并且被配置为控制被确定为对应于LC谐振电路的时间常数的输出时钟信号的频率， 涉及时间脉冲转换信号，其中根据参考时钟信号和分频时钟信号之间的相位差的变化连续地控制改变的电容的维持时间。
-
公开(公告)号：US20170201259A1
公开(公告)日：2017-07-13
申请号：US15273764
申请日：2016-09-23
Inventor： Ja Yol LEE , Min Jae LEE , Cheon Soo KIM , Min Uk HEO
CPC classification number: H03L7/0991 , H03L7/081 , H03L7/085 , H03L7/091 , H03L7/093 , H03L7/18 , H03L7/183
Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.
-
公开(公告)号：US20140266354A1
公开(公告)日：2014-09-18
申请号：US14028707
申请日：2013-09-17
Inventor： Hyun Ho BOO , Byung Hun MIN , Duong Quoc HOANG , Cheon Soo KIM , Hyun Kyu YU
IPC: H03L7/08
Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.
Abstract translation: 公开了一种数字锁相环，包括：时间数字转换器（TDC），被配置为基于输入时钟和参考时钟输出数字位，其中TDC包括：第一仲裁器组，其被配置为补偿 对于具有第一平均偏移的输入时钟和参考时钟之间的相位差，并输出第一逻辑值; 第二仲裁器组，被配置为用第二平均偏移补偿所述输入时钟和所述参考时钟之间的相位差，并输出第二逻辑值; 以及信号处理器，被配置为基于第一和第二逻辑值输出数字位。
-
公开(公告)号：US20160277049A1
公开(公告)日：2016-09-22
申请号：US15074881
申请日：2016-03-18
Inventor： Dong Woo KANG , Cheon Soo KIM , Jang Hong CHOI
CPC classification number: H04B1/0483 , H04B1/0053 , H04B2001/0491
Abstract: Provided is a transmitter. The transmitter includes a signal combiner configured to amplify a first differential radio frequency (RF) signal modulated to be transmitted through a first frequency band and a second differential RF signal modulated to be transmitted through a second frequency band non-adjacent to the first frequency band and summate the amplified first differential RF signal and the amplified second differential RF signal in a current mode to generate an RF signal and a power amplifier configured to amplify the generated RF signal.
Abstract translation: 提供一个发射机。 发射机包括信号组合器，其被配置为放大被调制为经由第一频带传输的第一差分射频（RF）信号和被调制以通过与第一频带不相邻的第二频带传输的第二差分RF信号 并且在当前模式下将放大的第一差分RF信号和放大的第二差分RF信号相加以产生RF信号，以及配置成放大所产生的RF信号的功率放大器。
-
公开(公告)号：US20150207233A1
公开(公告)日：2015-07-23
申请号：US14337907
申请日：2014-07-22
Inventor： Dong Young KIM , Jong Won LIM , Cheon Soo KIM
CPC classification number: H01Q9/0485
Abstract: Disclosed is a dielectric resonator antenna. The dielectric resonator antenna includes: a dielectric resonator; an antenna layer formed inside the dielectric resonator, and including a plurality of vias positioned at a surrounding area of the dielectric resonator; a metal pattern forming an opened surface in an upper portion of the antenna layer; a dielectric layer configured to cover the metal pattern on the dielectric resonator; an internal ground pattern including a coupling aperture for inputting a signal into the dielectric resonator under the dielectric resonator; and a feeding layer including a strip transmission line for transmitting a signal to the dielectric resonator, and positioned under the antenna layer.
Abstract translation: 公开了一种介质谐振器天线。 介质谐振器天线包括：介质谐振器; 形成在介质谐振器内的天线层，并且包括位于介电谐振器的周围区域的多个通孔; 金属图案，在天线层的上部形成开放面; 介电层，被配置为覆盖介质谐振器上的金属图案; 内部接地图案，包括用于将信号输入介质谐振器下的介质谐振器的耦合孔; 以及馈电层，其包括用于将信号传输到介质谐振器并位于天线层下方的带状传输线。
-
-
-
-
-
-
Search Results
7
records
(took 0.018 seconds)
