PORTABLE WIRELESS NODE AUXILIARY RELAY
    1.
    发明申请
    PORTABLE WIRELESS NODE AUXILIARY RELAY 有权
    便携式无线节点辅助继电器

    公开(公告)号:US20140349569A1

    公开(公告)日:2014-11-27

    申请号:US13956107

    申请日:2013-07-31

    IPC分类号: H04W16/26 H04B7/155

    摘要: Disclosed herein are example embodiments for portable wireless node auxiliary relay. For certain example embodiments, at least one device, such as an auxiliary relay item: (i) may serve as a relay between a portable wireless node and a fixed wireless node; or (ii) may communicate with at least one of a portable wireless node or a fixed wireless node using one or more antenna assembly configuration parameters that are associated with at least one orientation position. However, claimed subject matter is not limited to any particular described embodiments, implementations, examples, or so forth.

    摘要翻译: 这里公开了便携式无线节点辅助继电器的示例实施例。 对于某些示例性实施例,至少一个设备,例如辅助中继项:(i)可以用作便携式无线节点和固定无线节点之间的中继; 或者(ii)可以使用与至少一个取向位置相关联的一个或多个天线组件配置参数与便携式无线节点或固定无线节点中的至少一个进行通信。 然而,所要求保护的主题不限于任何特定的描述的实施例,实施方式,示例等。

    FLEXIBLE PROCESSORS AND FLEXIBLE MEMORY
    2.
    发明申请
    FLEXIBLE PROCESSORS AND FLEXIBLE MEMORY 有权
    灵活处理器和灵活的存储器

    公开(公告)号:US20140136755A1

    公开(公告)日:2014-05-15

    申请号:US13691448

    申请日:2012-11-30

    IPC分类号: G06F12/02

    摘要: An apparatus includes but is not limited to a non-volatile memory array and a processor integrated with the apparatus. The processor is operable to operate in combination with the non-volatile memory array to accumulate information associated with a product. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure.

    摘要翻译: 一种装置包括但不限于与该装置集成的非易失性存储器阵列和处理器。 处理器可操作以与非易失性存储器阵列组合操作以累积与产品相关联的信息。 除了上述之外,其他方面在形成本公开的一部分的权利要求,附图和文本中描述。

    Behavioral Fingerprinting Via Inferred Personal Relation
    3.
    发明申请
    Behavioral Fingerprinting Via Inferred Personal Relation 有权
    通过推测个人关系行为指纹

    公开(公告)号:US20140123253A1

    公开(公告)日:2014-05-01

    申请号:US13665830

    申请日:2012-10-31

    IPC分类号: G06F21/45

    CPC分类号: G06F21/316 G06F2221/2111

    摘要: Disclosed herein are example embodiments for behavioral fingerprinting via inferred personal relation. For certain example embodiments, at least one indication of personal relation for at least one authorized user may be inferred via at least one user-device interaction, and the at least one indication of personal relation may be incorporated into at least one behavioral fingerprint that is associated with the at least one authorized user, with the at least one behavioral fingerprint including one or more indicators of utilization of one or more user devices by the at least one authorized user.

    摘要翻译: 这里公开了通过推断的个人关系进行行为指纹的示例实施例。 对于某些示例实施例,可以经由至少一个用户 - 设备交互来推断至少一个授权用户的个人关系的至少一个指示,并且个人关系的至少一个指示可以被合并到至少一个行为指纹 与所述至少一个授权用户相关联,所述至少一个行为指纹包括由所述至少一个授权用户使用一个或多个用户设备的一个或多个指示符。

    Memory circuitry including computational circuitry for performing supplemental functions
    7.
    发明授权
    Memory circuitry including computational circuitry for performing supplemental functions 有权
    存储器电路,包括用于执行补充功能的计算电路

    公开(公告)号:US09442854B2

    公开(公告)日:2016-09-13

    申请号:US13841042

    申请日:2013-03-15

    摘要: A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.

    摘要翻译: 计算机系统包括但不限于主处理电路,耦合到主处理电路的总线以及耦合到总线的存储器电路。 存储器电路与主处理电路物理分离。 存储器电路包括至少一个集成存储器电路和计算电路。 所述至少一个集成存储器电路被配置为存储和检索数据,并且在访问间隔期间向所述总线提供所述主处理电路的请求数据。 与至少一个集成存储器电路共同定位的计算电路,与集成存储器电路共址的计算电路可以被配置为至少部分地在不访问间隔的时间段期间执行补充功能。

    PORTABLE WIRELESS NODE LOCAL COOPERATION
    8.
    发明申请
    PORTABLE WIRELESS NODE LOCAL COOPERATION 有权
    便利无线节点本地合作

    公开(公告)号:US20140349630A1

    公开(公告)日:2014-11-27

    申请号:US13945801

    申请日:2013-07-18

    IPC分类号: H04W24/02

    CPC分类号: H04W24/02 H04B7/026

    摘要: Disclosed herein are example embodiments for local cooperation between or among portable wireless nodes. For certain example embodiments, at least one device, such as a portable wireless node: (i) may identify at least one cooperative portable wireless node to participate in an antenna assembly configuration parameter architecture; or (ii) may communicate with at least one cooperative portable wireless node to share one or more antenna assembly configuration parameters that are associated with at least one orientation position of at least one portable wireless node. However, claimed subject matter is not limited to any particular described embodiments, implementations, examples, or so forth.

    摘要翻译: 这里公开了用于便携式无线节点之间或之间的本地协作的示例实施例。 对于某些示例实施例,诸如便携式无线节点的至少一个设备:(i)可以标识至少一个协作便携式无线节点以参与天线组件配置参数架构; 或者(ii)可以与至少一个协作便携式无线节点通信以共享与至少一个便携式无线节点的至少一个定向位置相关联的一个或多个天线组件配置参数。 然而,所要求保护的主题不限于任何特定的描述的实施例,实施方式,示例等。

    MULTI-CORE PROCESSING IN MEMORY
    10.
    发明申请
    MULTI-CORE PROCESSING IN MEMORY 审中-公开
    内存中的多核处理

    公开(公告)号:US20140137119A1

    公开(公告)日:2014-05-15

    申请号:US13738788

    申请日:2013-01-10

    IPC分类号: G06F9/46

    CPC分类号: G06F9/46 G06F21/56

    摘要: A memory device includes but is not limited to a substrate, a non-volatile memory array integrated on the substrate, and processing logic integrated with the non-volatile memory array on the substrate. The processing logic is operable to perform at least one general purpose processing function associated with the non-volatile memory array.

    摘要翻译: 存储器件包括但不限于衬底,集成在衬底上的非易失性存储器阵列以及与衬底上的非易失性存储器阵列集成的处理逻辑。 处理逻辑可操作以执行与非易失性存储器阵列相关联的至少一个通用处理功能。