公开(公告)号：US10044496B2

公开(公告)日：2018-08-07

申请号：US15101935

申请日：2014-03-21

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Nagi Mekhiel

IPC: H04L7/00 ,  G06F1/04 ,  H03K5/15 ,  H04L12/40

Abstract: Technologies are generally described herein for bandwidth amplification using a pre-clock signal to latch data at a latch in an input register of a sender section while passing the data through a multiplexer of the sender section in a serial manner. In some configurations, pre-clocking the multiplexer can allow for parallel operations to occur within the sender section, thus hiding or reducing the effects of certain serialization delays associated with the multiplexer. Furthermore, the pre-clocking of the multiplexer, in some configurations, hides or reduces the register latch hold and setup delays. A method may create three levels of parallelization of latencies between a sender circuit, a serialization circuit, and a receiver circuit by overlapping them at same time.

公开(公告)号：US20160180916A1

公开(公告)日：2016-06-23

申请号：US14579239

申请日：2014-12-22

Applicant: Empire Technology Development LLC

Inventor： Nagi Mekhiel

IPC: G11C11/406 ,  G11C7/06 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4091

CPC classification number: G11C11/4087 ,  G11C7/1039 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2209

Abstract: Technologies are generally described herein for a reconfigurable row dynamic random access memory device. The reconfigurable row may correspond to a logically addressable row, where multiple row segments can be mapped to different physical DRAM rows. In some examples, a reconfigurable row dynamic random access memory may use a row segment activator to allow memory operation access to a row segment, while maintaining the remaining part of the same row available for other memory access operations. The reconfigurable row dynamic random access memory may be operated in various modes of operation, including a pipeline mode and a burst mode.

Abstract translation: 这里通常描述了用于可重新配置的行动态随机存取存储器设备的技术。 可重配置行可以对应于可逻辑寻址的行，其中多个行段可被映射到不同的物理DRAM行。 在一些示例中，可重新配置的行动态随机存取存储器可以使用行段激活器来允许存储器操作访问行段，同时保持同一行的剩余部分可用于其他存储器访问操作。 可重构行动态随机存取存储器可以在各种操作模式下操作，包括流水线模式和突发模式。

公开(公告)号：US09734889B2

公开(公告)日：2017-08-15

申请号：US14579239

申请日：2014-12-22

Applicant: Empire Technology Development LLC

Inventor： Nagi Mekhiel

IPC: G06F12/00 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C7/1039 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2209

Abstract: Technologies are generally described herein for a reconfigurable row dynamic random access memory device. The reconfigurable row may correspond to a logically addressable row, where multiple row segments can be mapped to different physical DRAM rows. In some examples, a reconfigurable row dynamic random access memory may use a row segment activator to allow memory operation access to a row segment, while maintaining the remaining part of the same row available for other memory access operations. The reconfigurable row dynamic random access memory may be operated in various modes of operation, including a pipeline mode and a burst mode.

公开(公告)号：US20160308666A1

公开(公告)日：2016-10-20

申请号：US15101935

申请日：2014-03-21

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Nagi Mekhiel

IPC: H04L7/00 ,  G06F1/04 ,  H04L12/40

CPC classification number: H04L7/0091 ,  G06F1/04 ,  H03K5/15066 ,  H04L7/0008 ,  H04L12/4013

Abstract: Technologies are generally described herein for bandwidth amplification using a pre-clock signal to latch data at a latch in an input register of a sender section while passing the data through a multiplexer of the sender section in a serial manner. In some configurations, pre-clocking the multiplexer can allow for parallel operations to occur within the sender section, thus hiding or reducing the effects of certain serialization delays associated with the multiplexer. Furthermore, the pre-clocking of the multiplexer, in some configurations, hides or reduces the register latch hold and setup delays. A method may create three levels of parallelization of latencies between a sender circuit, a serialization circuit, and a receiver circuit by overlapping them at same time.

Abstract translation: 这里通常使用前时钟信号来描述带宽放大的技术，以便在发送器部分的输入寄存器中的锁存器处锁存数据，同时以串行方式传送数据通过发送器部分的多路复用器。 在一些配置中，预分配多路复用器可以允许在发送器部分内发生并行操作，从而隐藏或减少与多路复用器相关联的某些串行化延迟的影响。 此外，在一些配置中，多路复用器的预时钟隐藏或减少寄存器锁存器保持和建立延迟。 一种方法可以在发送器电路，串行化电路和接收器电路之间通过在同一时间重叠来产生延迟并行化的三个级别。