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公开(公告)号：US07454727B1
公开(公告)日：2008-11-18
申请号：US11423575
申请日：2006-06-12
CPC分类号： G06F17/504
摘要： Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior. Such assumptions are converted, with the use of logic synthesis tools, into a gate-level representation. For formal verification, a verification output is constructed from the gate-level representation and DUT/DUV assertion-monitoring circuitry. A formal verifier seeks to prove the verification output cannot indicate a design error. For simulation verification, the gate-level representation is converted into a hybrid representation comprising pipelines and combinational constraints. During simulation, the pipelines hold state information necessary for a solution, of the combinational constraints, to be in accord with the sequential assumption constraints. For certain sequential assumption constraints, the combinational constraints are insufficient to insure avoidance of deadend states. In a deadend state, an assumption is violated. A method is presented for augmenting the combinational constraints to avoid deadend states.
摘要翻译： 关于自动转换假设约束，用于电路设计验证，为测试DUT / DUV建立环境，其中假设指定顺序行为。 通过使用逻辑综合工具将这些假设转换为门级表示。 对于形式验证，验证输出由门级表示和DUT / DUV断言监视电路构成。 正式验证者试图证明验证输出不能指示设计错误。 对于模拟验证，门级表示被转换成包括流水线和组合约束的混合表示。 在模拟期间，管线将组合约束的解决方案所需的状态信息与顺序假设约束保持一致。 对于某些顺序假设约束，组合约束不足以确保避免死区状态。 在死刑状态下，违反了假设。 提出了一种用于增加组合约束以避免死机状态的方法。
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公开(公告)号：US07076753B2
公开(公告)日：2006-07-11
申请号：US10740033
申请日：2003-12-18
CPC分类号： G06F17/504
摘要： Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior. Such assumptions are converted, with the use of logic synthesis tools, into a gate-level representation. For formal verification, a verification output is constructed from the gate-level representation and DUT/DUV assertion-monitoring circuitry. A formal verifier seeks to prove the verification output cannot indicate a design error. For simulation verification, the gate-level representation is converted into a hybrid representation comprising pipelines and combinational constraints. During simulation, the pipelines hold state information necessary for a solution, of the combinational constraints, to be in accord with the sequential assumption constraints. For certain sequential assumption constraints, the combinational constraints are insufficient to insure avoidance of deadend states. In a deadend state, an assumption is violated. A method is presented for augmenting the combinational constraints to avoid deadend states.
摘要翻译： 关于自动转换假设约束，用于电路设计验证，为测试DUT / DUV建立环境，其中假设指定顺序行为。 通过使用逻辑综合工具将这些假设转换为门级表示。 对于形式验证，验证输出由门级表示和DUT / DUV断言监视电路构成。 正式验证者试图证明验证输出不能指示设计错误。 对于模拟验证，门级表示被转换成包括流水线和组合约束的混合表示。 在模拟期间，管线将组合约束的解决方案所需的状态信息与顺序假设约束保持一致。 对于某些顺序假设约束，组合约束不足以确保避免死区状态。 在死刑状态下，违反了假设。 提出了一种用于增加组合约束以避免死机状态的方法。
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公开(公告)号：US20050138585A1
公开(公告)日：2005-06-23
申请号：US10740033
申请日：2003-12-18
申请人： Eduard Cerny , Ashvin Dsouza , Kevin Harer , Pei-Hsin Ho
发明人： Eduard Cerny , Ashvin Dsouza , Kevin Harer , Pei-Hsin Ho
CPC分类号： G06F17/504
摘要： Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior. Such assumptions are converted, with the use of logic synthesis tools, into a gate-level representation. For formal verification, a verification output is constructed from the gate-level representation and DUT/DUV assertion-monitoring circuitry. A formal verifier seeks to prove the verification output cannot indicate a design error. For simulation verification, the gate-level representation is converted into a hybrid representation comprising pipelines and combinational constraints. During simulation, the pipelines hold state information necessary for a solution, of the combinational constraints, to be in accord with the sequential assumption constraints. For certain sequential assumption constraints, the combinational constraints are insufficient to insure avoidance of deadend states. In a deadend state, an assumption is violated. A method is presented for augmenting the combinational constraints to avoid deadend states.
摘要翻译： 关于自动转换假设约束，用于电路设计验证，为测试DUT / DUV建立环境，其中假设指定顺序行为。 通过使用逻辑综合工具将这些假设转换为门级表示。 对于形式验证，验证输出由门级表示和DUT / DUV断言监视电路构成。 正式验证者试图证明验证输出不能指示设计错误。 对于模拟验证，门级表示被转换成包括流水线和组合约束的混合表示。 在模拟期间，管线将组合约束的解决方案所需的状态信息与顺序假设约束保持一致。 对于某些顺序假设约束，组合约束不足以确保避免死区状态。 在死刑状态下，违反了假设。 提出了一种用于增加组合约束以避免死机状态的方法。
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4.发明授权Method and apparatus for determining the timing of an integrated circuit design 有权用于确定集成电路设计的定时的方法和装置公开(公告)号：US07984405B2
公开(公告)日：2011-07-19
申请号：US11972521
申请日：2008-01-10
申请人： Yiu-Chung Mang , Pei-Hsin Ho
发明人： Yiu-Chung Mang , Pei-Hsin Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system that determines the timing of an integrated circuit (IC) design is presented. During operation, the system receives a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design. Next, the system estimates capacitances for cells within the IC design based on analytic models of the cells. The system then estimates the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein the post-physical-optimization timing is estimated without performing physical optimization.
摘要翻译： 介绍了一种确定集成电路（IC）设计时序的系统。 在操作期间，系统接收IC设计的网表，其中网表指定IC设计内的单元的放置。 接下来，系统基于单元的分析模型估计IC设计中的单元的电容。 然后，系统基于网表，电容和分析模型来估计IC设计的物理后优化时序，其中在不执行物理优化的情况下估计后物理优化定时。
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公开(公告)号：US20080250376A1
公开(公告)日：2008-10-09
申请号：US11732848
申请日：2007-04-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/504
摘要： One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes.
摘要翻译： 本发明的一个实施例提供了一种在集成电路（IC）芯片的设计期间路由一组点对的系统。 该系统包括路由引擎，其被配置为搜索路径以连接该组对点中的当前点对，其中该路径包括一组矩形和顶点。 路由引擎使用路由数据库，其跟踪可阻碍当前对点对的路由的先前路由网络。 该系统还包括能够求解一组约束的可满足性（SAT）求解器，其中所述约束集合与所述一组点对的可路由性相关联。 SAT求解器还包括一个SAT数据库，该数据库维护一组约束，并且对该组约束的当前部分解决方案。 如果当前部分解决方案发生变化，SAT数据库将用于更新路由数据库。
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公开(公告)号：US07260802B2
公开(公告)日：2007-08-21
申请号：US11159950
申请日：2005-06-23
申请人： Pei-Hsin Ho , Yongseok Cheon
发明人： Pei-Hsin Ho , Yongseok Cheon
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A system that partitions an integrated circuit. First, the system receives a placement for an integrated circuit. The system then calculates a joint-utilization ratio for pairs of logic modules in the placement. Next, the system sorts the pairs of logic modules based on the joint-utilization ratio. The system then selects top pairs of logic modules based on the joint-utilization ratio and clusters the top pairs of logic modules into new partitions.
摘要翻译： 分离集成电路的系统。 首先，系统接收集成电路的放置。 然后，该系统在该位置中计算逻辑模块对的联合利用率。 接下来，系统基于联合利用率对逻辑模块对进行排序。 然后，该系统基于联合利用率选择最上面的逻辑模块对，并将顶层的逻辑模块对集群成新的分区。
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7.发明申请Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip 有权用于为集成电路芯片生成可变容错时钟树的方法和装置公开(公告)号：US20080168412A1
公开(公告)日：2008-07-10
申请号：US11652302
申请日：2007-01-10
申请人： Yongseok Cheon , Pei-Hsin Ho
发明人： Yongseok Cheon , Pei-Hsin Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/10 , G06F2217/62
摘要： One embodiment of the present invention relates to a process that generates a clock-tree on an integrated circuit (IC) chip. During operation, the process starts by receiving a placement for a chip layout, where the placement includes a set of registers at fixed locations in the chip layout. The process then generates a timing criticality profile for the set of registers, wherein the timing criticality profile specifies timing criticalities between pairs of registers in the set of registers. Next, the process clusters the set of registers based on the timing criticality profile to create a clock-tree for the set of registers. By clustering the registers based on the timing criticality profile, the process facilitates using commonly-shared clock paths in the clock-tree to provide clock signals to timing critical register pairs.
摘要翻译： 本发明的一个实施例涉及在集成电路（IC）芯片上产生时钟树的过程。 在操作期间，该过程通过接收芯片布局的放置开始，其中放置包括在芯片布局中的固定位置处的一组寄存器。 该过程然后为该组寄存器生成定时关键性曲线，其中定时关键性曲线规定了寄存器组中的寄存器对之间的定时关键性。 接下来，该过程基于时间关键性简档来聚集寄存器组，以为该组寄存器创建时钟树。 通过基于时序临界概况对寄存器进行聚类，该过程有助于在时钟树中使用共享共享时钟路径，为定时关键寄存器对提供时钟信号。
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公开(公告)号：US20060101365A1
公开(公告)日：2006-05-11
申请号：US11159950
申请日：2005-06-23
申请人： Pei-Hsin Ho , Yongseok Cheon
发明人： Pei-Hsin Ho , Yongseok Cheon
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A system that partitions an integrated circuit. First, the system receives a placement for an integrated circuit. The system then calculates a joint-utilization ratio for pairs of logic modules in the placement. Next, the system sorts the pairs of logic modules based on the joint-utilization ratio. The system then selects top pairs of logic modules based on the joint-utilization ratio and clusters the top pairs of logic modules into new partitions.
摘要翻译： 分离集成电路的系统。 首先，系统接收集成电路的放置。 然后，该系统在该位置中计算逻辑模块对的联合利用率。 接下来，系统基于联合利用率对逻辑模块对进行排序。 然后，该系统基于联合利用率选择最上面的逻辑模块对，并将顶层的逻辑模块对集群成新的分区。
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公开(公告)号：US20110126167A1
公开(公告)日：2011-05-26
申请号：US12625392
申请日：2009-11-24
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output.
摘要翻译： 提供了多模式冗余删除方法。 在这种方法中，访问设计后，可以开始使用故障模拟进行全面的冗余删除。 当执行全尺寸冗余删除的预定周期已经达到第一截止时，则该方法可以确定设计的临时输出的位置，创建临时输出，并执行到临时输出的局部冗余去除 。 可以输出基于全面冗余删除和局部冗余删除的优化设计。
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10.发明授权公开(公告)号：US07469392B2
公开(公告)日：2008-12-23
申请号：US11298120
申请日：2005-12-08
申请人： Yiu Chung Mang , Pei-Hsin Ho
发明人： Yiu Chung Mang , Pei-Hsin Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： One embodiment of the present invention provides a system that refines an abstract model. Note that abstraction refinement is commonly used in formal property verification. During operation, the system receives an abstract model which is a subset of a logic design which can be represented using a set of variables and a set of Boolean functions. Next, the system receives a safety property for the logic design which is desired to be proven. The system also receives a set of counter-examples. A counter-example is a sequence of states that violates the safety property. Note that a state is an assignment of values to the variables, which are determined using the set of Boolean functions and the variable values in the previous state. The system then determines a set of cooperative variables using the set of counter-examples. A cooperative variable is a variable that can help invalidate all counter-examples. The system then refines the abstract model using the set of cooperative variables.
摘要翻译： 本发明的一个实施例提供了一种改进抽象模型的系统。 请注意，抽象精简通常用于形式属性验证。 在操作期间，系统接收抽象模型，该抽象模型是可以使用一组变量和一组布尔函数来表示的逻辑设计的子集。 接下来，系统接收要被证明的逻辑设计的安全属性。 该系统还接收一组反例。 反例是违反安全属性的一系列状态。 请注意，状态是赋值给变量的值，它们使用布尔函数集和前一个状态中的变量值来确定。 然后，系统使用一组反例来确定一组协作变量。 合作变量是一个可以帮助无效所有反例的变量。 然后，系统使用一组合作变量来提炼抽象模型。
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